P
Patrick
Guest
Hello,
I'm designing a dqpsk modem in VHDL. The data rate is 4 Mbps, so 2MHZ
bandwidth (2Mbauds in QPSK). And after the DQPSK mapping I use a RRC
Filter operating at 8 MSps and then interpolation by 2 and by 5 to
have a sampling frequency of 80 MSps. That work good in VHDL and in
synthesis.
Now I would like to reduce the filter size because I have 6 filters.
I'm trying to implant a polyphase filter which can reduce the size of
the filter.
For example, the RRC filter is a 24 taps filter which can be reduced
to 6 taps because there's 3 samples with zero value at the input of
this filter and so the polyphase filter don't do the zero
multiplication.
Do you have suggestion about this project ?
thanks to all the vhdl'designer...
I'm designing a dqpsk modem in VHDL. The data rate is 4 Mbps, so 2MHZ
bandwidth (2Mbauds in QPSK). And after the DQPSK mapping I use a RRC
Filter operating at 8 MSps and then interpolation by 2 and by 5 to
have a sampling frequency of 80 MSps. That work good in VHDL and in
synthesis.
Now I would like to reduce the filter size because I have 6 filters.
I'm trying to implant a polyphase filter which can reduce the size of
the filter.
For example, the RRC filter is a 24 taps filter which can be reduced
to 6 taps because there's 3 samples with zero value at the input of
this filter and so the polyphase filter don't do the zero
multiplication.
Do you have suggestion about this project ?
thanks to all the vhdl'designer...