Polyphase filter

M

Martin Euredjian

Guest
Working on a polyphase decimator and interpolator. I'm trying to use the
same chunk-o-logic to implement both functions. In either case, it is
easiest to drive the control logic from the fastest of the two clocks. I'm
trying to figure out the most elegant way to achieve this. Any thoughts,
ideas, links?

Thanks,

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<S46Yb.24448$9T5.5086@newssvr27.news.prodigy.com>...
Working on a polyphase decimator and interpolator. I'm trying to use the
same chunk-o-logic to implement both functions. In either case, it is
easiest to drive the control logic from the fastest of the two clocks. I'm
trying to figure out the most elegant way to achieve this. Any thoughts,
ideas, links?

Thanks,
Click to expand...
If you can work this out, it would be the easiest:

Say you have a set of frequencies you want to handle:

{f1, f2, f3, f4...fn}

Clock your control logic at a frequency that can generate all of these
other frequencies. E.g., for {2,3,5,6 whateverHz}, select your
control clock to be 30 whateverHz. To clock data in or out of the
decimator/interpolators, use clock enables that are synchronous to the
data and the control clock but have a duration of 1 control clock.

Slightly off topic, but if you're doing this fixed point, you might
have to adjust gains depending on input and output rate for consistent
scaling.
 
if you intend to implement the filter in an FPGA, it will be a pain to have
so many derived clocks.
if you do partial reconfiguration, the probability of P&R trouble can be
very high...

just my 2c...

Kelvin



"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0402280111.14a14564@posting.google.com...
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:<S46Yb.24448$9T5.5086@newssvr27.news.prodigy.com>...
Working on a polyphase decimator and interpolator. I'm trying to use
the
same chunk-o-logic to implement both functions. In either case, it is
easiest to drive the control logic from the fastest of the two clocks.
I'm
trying to figure out the most elegant way to achieve this. Any
thoughts,
ideas, links?

Thanks,

If you can work this out, it would be the easiest:

Say you have a set of frequencies you want to handle:

{f1, f2, f3, f4...fn}

Clock your control logic at a frequency that can generate all of these
other frequencies. E.g., for {2,3,5,6 whateverHz}, select your
control clock to be 30 whateverHz. To clock data in or out of the
decimator/interpolators, use clock enables that are synchronous to the
data and the control clock but have a duration of 1 control clock.

Slightly off topic, but if you're doing this fixed point, you might
have to adjust gains depending on input and output rate for consistent
scaling.
Click to expand...
 
Clock enables are your friend. The processing of the samples does not have to
be spaced equally in time. All that matters is that the samples are spaced
equally when converting to/from analog. For example, if the sampling is at
15/16 of the filter's clock, you can disable the filter for one clock in 16.
It makes the filtering much easier with multiple sample rates if the whole
filter ban is running off a single clock. With bit serial filters, you get
even more flexibility.

"Kelvin @ SG" wrote:

if you intend to implement the filter in an FPGA, it will be a pain to have
so many derived clocks.
if you do partial reconfiguration, the probability of P&R trouble can be
very high...

just my 2c...

Kelvin

"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0402280111.14a14564@posting.google.com...
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:<S46Yb.24448$9T5.5086@newssvr27.news.prodigy.com>...
Working on a polyphase decimator and interpolator. I'm trying to use
the
same chunk-o-logic to implement both functions. In either case, it is
easiest to drive the control logic from the fastest of the two clocks.
I'm
trying to figure out the most elegant way to achieve this. Any
thoughts,
ideas, links?

Thanks,

If you can work this out, it would be the easiest:

Say you have a set of frequencies you want to handle:

{f1, f2, f3, f4...fn}

Clock your control logic at a frequency that can generate all of these
other frequencies. E.g., for {2,3,5,6 whateverHz}, select your
control clock to be 30 whateverHz. To clock data in or out of the
decimator/interpolators, use clock enables that are synchronous to the
data and the control clock but have a duration of 1 control clock.

Slightly off topic, but if you're doing this fixed point, you might
have to adjust gains depending on input and output rate for consistent
scaling.
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
He didn't say how many frequencies he was going to use, or what kind
of FPGA, or how many bits in the samples. But even if he had 20
different frequencies, you could do all in a single FPGA and use a
provisioned register to select the input and output chip enable rates,
as well as the frequency dedendant filter gains (if any).

"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<c1ppdl$d3v$1@reader01.singnet.com.sg>...
if you intend to implement the filter in an FPGA, it will be a pain to have
so many derived clocks.
if you do partial reconfiguration, the probability of P&R trouble can be
very high...

just my 2c...

Kelvin



"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0402280111.14a14564@posting.google.com...
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:<S46Yb.24448$9T5.5086@newssvr27.news.prodigy.com>...
Working on a polyphase decimator and interpolator. I'm trying to use
the
same chunk-o-logic to implement both functions. In either case, it is
easiest to drive the control logic from the fastest of the two clocks.
I'm
trying to figure out the most elegant way to achieve this. Any
thoughts,
ideas, links?

Thanks,

If you can work this out, it would be the easiest:

Say you have a set of frequencies you want to handle:

{f1, f2, f3, f4...fn}

Clock your control logic at a frequency that can generate all of these
other frequencies. E.g., for {2,3,5,6 whateverHz}, select your
control clock to be 30 whateverHz. To clock data in or out of the
decimator/interpolators, use clock enables that are synchronous to the
data and the control clock but have a duration of 1 control clock.

Slightly off topic, but if you're doing this fixed point, you might
have to adjust gains depending on input and output rate for consistent
scaling.
Click to expand...
 
William Wallace wrote:

He didn't say how many frequencies he was going to use, or what kind
of FPGA, or how many bits in the samples.
Click to expand...
A few frequencies. Not enough data yet.
Samples can be up to 16 bits wide x 3 (RGB image processing).
Virtex 2V1000.

Had to put the project on the shelf for a few days. I'm very tempted to run
the whole thing at the highest possible frequency (in the context of what
needs to be done, not the highest attainable by the FPGA) and use clock
enables. It would seem to me that this is the easiest way to stay out of
trouble. I like that.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
Well, if it makes economic sense to hire a consultant, let me know,
the firm I work at can help.

"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<oNk0c.18489$jR7.10085@newssvr29.news.prodigy.com>...
William Wallace wrote:

He didn't say how many frequencies he was going to use, or what kind
of FPGA, or how many bits in the samples.

A few frequencies. Not enough data yet.
Samples can be up to 16 bits wide x 3 (RGB image processing).
Virtex 2V1000.

Had to put the project on the shelf for a few days. I'm very tempted to run
the whole thing at the highest possible frequency (in the context of what
needs to be done, not the highest attainable by the FPGA) and use clock
enables. It would seem to me that this is the easiest way to stay out of
trouble. I like that.
Click to expand...
 
I'll definetly keep that in mind. We have a lot coming up over the next few
months. Please provide me with additional info privately.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"


"William Wallace" <msm30@yahoo.com> wrote in message
news:7e4865b7.0403052155.49009db7@posting.google.com...
Well, if it makes economic sense to hire a consultant, let me know,
the firm I work at can help.

"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:<oNk0c.18489$jR7.10085@newssvr29.news.prodigy.com>...
William Wallace wrote:

He didn't say how many frequencies he was going to use, or what kind
of FPGA, or how many bits in the samples.

A few frequencies. Not enough data yet.
Samples can be up to 16 bits wide x 3 (RGB image processing).
Virtex 2V1000.

Had to put the project on the shelf for a few days. I'm very tempted to
run
the whole thing at the highest possible frequency (in the context of
what
needs to be done, not the highest attainable by the FPGA) and use clock
enables. It would seem to me that this is the easiest way to stay out
of
trouble. I like that.
Click to expand...
 
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