PLL simulation question

[Adam]

Hi Friends,


I am designing a PLL. I am designing the analog parts of PLL
manually. And I am using a standard library for the digital parts.
I found that the digital cells do not contain the information of
spice, netlist or layout. They are for front end simulation only.

My question is how can I do the simulation of the whole PLL in
virtuoso without the information of spice, netlist and layout in
virtuoso
Am I supposed to use some other tool?

Thanks.

Adam

 

[S. Badel]

Adam wrote:

Hi Friends,


I am designing a PLL. I am designing the analog parts of PLL
manually. And I am using a standard library for the digital parts.
I found that the digital cells do not contain the information of
spice, netlist or layout. They are for front end simulation only.

My question is how can I do the simulation of the whole PLL in
virtuoso without the information of spice, netlist and layout in
virtuoso
Am I supposed to use some other tool?

Thanks.

Adam

Hello,

what you want is a mixed-signal simulator. Cadence's is called AMS Designer. It will use spectre or
ultrasim to simulate the analog parts of your design, and the ius simulator to simulate the digital
parts.

There's of course a lot of documentation on the topic, I'm just giving a few hints :

"Virtuoso AMS Environment User Guide"

"Running the Virtuoso AMS Designer Simulator from the Analog Design Environment and the Hierarchy
Editor"


Another option is to obtain backend views for your library cells, and simulate the complete thing
analog...

Good luck,
Stéphane

 

[Andrew Beckett]

Adam wrote, on 09/10/08 21:52:

Hi Friends,


I am designing a PLL. I am designing the analog parts of PLL
manually. And I am using a standard library for the digital parts.
I found that the digital cells do not contain the information of
spice, netlist or layout. They are for front end simulation only.

My question is how can I do the simulation of the whole PLL in
virtuoso without the information of spice, netlist and layout in
virtuoso
Am I supposed to use some other tool?

Thanks.

Adam

What representations of the standard cells do you have? Verilog? Do
you have SPICE in a separate file?

Andrew.

 

[Adam]

Stephane,

Thank you for your information.


Adam

S. Badel wrote:

Adam wrote:
Hi Friends,


I am designing a PLL. I am designing the analog parts of PLL
manually. And I am using a standard library for the digital parts.
I found that the digital cells do not contain the information of
spice, netlist or layout. They are for front end simulation only.

My question is how can I do the simulation of the whole PLL in
virtuoso without the information of spice, netlist and layout in
virtuoso
Am I supposed to use some other tool?

Thanks.

Adam

Hello,

what you want is a mixed-signal simulator. Cadence's is called AMS Designer. It will use spectre or
ultrasim to simulate the analog parts of your design, and the ius simulator to simulate the digital
parts.

There's of course a lot of documentation on the topic, I'm just giving a few hints :

"Virtuoso AMS Environment User Guide"

"Running the Virtuoso AMS Designer Simulator from the Analog Design Environment and the Hierarchy
Editor"


Another option is to obtain backend views for your library cells, and simulate the complete thing
analog...

Good luck,
St�phane

 

[Adam]

Andrew,

I think there are only VHDL files(behavioral.asm, behavioral.dat)
and symbols(master.tag, symbol.cdb and pc.db).
According to the document, we don't have access to the spice files.

Thanks,
Adam



Andrew Beckett wrote:

Adam wrote, on 09/10/08 21:52:
Hi Friends,


I am designing a PLL. I am designing the analog parts of PLL
manually. And I am using a standard library for the digital parts.
I found that the digital cells do not contain the information of
spice, netlist or layout. They are for front end simulation only.

My question is how can I do the simulation of the whole PLL in
virtuoso without the information of spice, netlist and layout in
virtuoso
Am I supposed to use some other tool?

Thanks.

Adam

What representations of the standard cells do you have? Verilog? Do
you have SPICE in a separate file?

Andrew.