pll frequency multiplier

[Peter]

I'm just a beginner vhdl programmer. I'm doing a program for Altera
PLD about an LVDS Receiver. Unfortunately, the PLD I am using does not
support some altera function components like LVDS Receiver and PLL.
That's now my problem, is there someone knows a vhdl code of pll
frequency multiplier or even teach me how can I implement it into
code. for example I have an input clock with a frequency of 50MHz, I
need to generate a clock that is 7x of the input frequency (350MHz). I
can't generate that algorithm into code. Please help me on this....

thanks and best regards,

Peter

 

[Ray Andraka]

Ahh, so it is an altera device, and the device doesn't have those
components in it. You are pretty much out of luck. Either select a
device that has these components (they are not purely digital, you can't
use the regular prograamable fabric to make them), or use an external PLL
chip and LVDS translators. I don't think the devices without a PLL or
LVDS will handle a 350 MHz signal anyway.

Peter wrote:

I'm just a beginner vhdl programmer. I'm doing a program for Altera
PLD about an LVDS Receiver. Unfortunately, the PLD I am using does not
support some altera function components like LVDS Receiver and PLL.
That's now my problem, is there someone knows a vhdl code of pll
frequency multiplier or even teach me how can I implement it into
code. for example I have an input clock with a frequency of 50MHz, I
need to generate a clock that is 7x of the input frequency (350MHz). I
can't generate that algorithm into code. Please help me on this....

thanks and best regards,

Peter

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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
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