PLL dynamic phase shift...

Thread starter promach
Start date Nov 21, 2021

Nov 21, 2021

#1

P

promach

Guest

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency?

https://i.imgur.com/Rr1jS8Q.png

https://i.imgur.com/jgfvxk6.png

You must log in or register to reply here.

Share:

Facebook X (Twitter) Reddit Pinterest Tumblr WhatsApp Email Link

Welcome to EDABoard.com

Sponsor

This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.

Accept Learn more…

Top