PLL Cyclone III vs PLL(DLL) Spartan-3AN

[Eugen_pcad_ru]

Hello all!
I need pll which can:
1) 40 MHz -> 320 MHz (0 deg),
320 MHz (15 deg),
320 MHz (30 deg),
320 MHz (45 deg),
320 MHz (60 deg)
320 MHz (75 deg),
320 MHz (90 deg),
320 MHz (105 deg),
320 MHz (120 deg),
320 MHz (135 deg),
320 MHz (150 deg),
320 MHz (165 deg),
320 MHz (180 deg).
They can be together or not.
And I have two fpgas: Cyclone III (Altera), Spartan-3AN.
What fpga is better for me? Why? Or its no difference?

Thanks all for answers!



---------------------------------------
Posted through http://www.FPGARelated.com

 

[Tim Wescott]

On 02/28/2011 06:36 AM, Eugen_pcad_ru wrote:

Hello all!
I need pll which can:
1) 40 MHz -> 320 MHz (0 deg),
320 MHz (15 deg),
320 MHz (30 deg),
320 MHz (45 deg),
320 MHz (60 deg)
320 MHz (75 deg),
320 MHz (90 deg),
320 MHz (105 deg),
320 MHz (120 deg),
320 MHz (135 deg),
320 MHz (150 deg),
320 MHz (165 deg),
320 MHz (180 deg).
They can be together or not.
And I have two fpgas: Cyclone III (Altera), Spartan-3AN.
What fpga is better for me? Why? Or its no difference?

I don't know about the Altera part, but Xilinx is too cool to use
phase-locked loops -- they use delay-locked loops instead (see the data
sheet). This means that they can maybe generate the clock you need, but
they'll do it by delaying the 40MHz clock, and they'll demand that your
clock edges have no more than 150ps of jitter. In other words, you need
to feed it a 40MHz clock that jitters no worse than a good 320MHz clock.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

 

[Ed McGettigan]

On Feb 28, 11:32 am, Tim Wescott <t...@seemywebsite.com> wrote:

On 02/28/2011 06:36 AM, Eugen_pcad_ru wrote:





Hello all!
I need pll which can:
1) 40 MHz ->  320 MHz (0 deg),
              320 MHz (15 deg),
              320 MHz (30 deg),
              320 MHz (45 deg),
              320 MHz (60 deg)
              320 MHz (75 deg),
              320 MHz (90 deg),
              320 MHz (105 deg),
              320 MHz (120 deg),
              320 MHz (135 deg),
              320 MHz (150 deg),
              320 MHz (165 deg),
              320 MHz (180 deg).
They can be together or not.
And I have two fpgas: Cyclone III (Altera), Spartan-3AN.
What fpga is better for me? Why? Or its no difference?

I don't know about the Altera part, but Xilinx is too cool to use
phase-locked loops -- they use delay-locked loops instead (see the data
sheet).  This means that they can maybe generate the clock you need, but
they'll do it by delaying the 40MHz clock, and they'll demand that your
clock edges have no more than 150ps of jitter.  In other words, you need
to feed it a 40MHz clock that jitters no worse than a good 320MHz clock.

--

Tim Wescott
Wescott Design Serviceshttp://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details athttp://www.wescottdesign.com/actfes/actfes.html- Hide quoted text -

- Show quoted text -

In the Spartan-3A family the DCM CLKIN jitter is specified at +/-300pS
at 40 MHz.

but Xilinx is too cool to use phase-locked loops

While this is true for older families, Virtex-5, Virtex-6, and
Spartan-6 all include PLL clocking elements.

Ed McGettigan
--
Xilinx Inc.

 

[Tim Wescott]

On 03/01/2011 08:34 AM, Ed McGettigan wrote:

On Feb 28, 11:32 am, Tim Wescott<t...@seemywebsite.com> wrote:
On 02/28/2011 06:36 AM, Eugen_pcad_ru wrote:





Hello all!
I need pll which can:
1) 40 MHz -> 320 MHz (0 deg),
320 MHz (15 deg),
320 MHz (30 deg),
320 MHz (45 deg),
320 MHz (60 deg)
320 MHz (75 deg),
320 MHz (90 deg),
320 MHz (105 deg),
320 MHz (120 deg),
320 MHz (135 deg),
320 MHz (150 deg),
320 MHz (165 deg),
320 MHz (180 deg).
They can be together or not.
And I have two fpgas: Cyclone III (Altera), Spartan-3AN.
What fpga is better for me? Why? Or its no difference?

I don't know about the Altera part, but Xilinx is too cool to use
phase-locked loops -- they use delay-locked loops instead (see the data
sheet). This means that they can maybe generate the clock you need, but
they'll do it by delaying the 40MHz clock, and they'll demand that your
clock edges have no more than 150ps of jitter. In other words, you need
to feed it a 40MHz clock that jitters no worse than a good 320MHz clock.

In the Spartan-3A family the DCM CLKIN jitter is specified at +/-300pS
at 40 MHz.

By the data sheet that I looked at, that is true unless you're asking
for synthesized frequencies > 150MHz, in which case it needs to be 150ps.

but Xilinx is too cool to use phase-locked loops

While this is true for older families, Virtex-5, Virtex-6, and
Spartan-6 all include PLL clocking elements.

That's good to know -- sometimes a real PLL is a good thing, when you
have a clock to clean up.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

 

[Chris Maryan]

Generally a post of this sort begs the question: what are you doing and why do you think you need 15 degree phase increments of a 320MHz clock? Do you need them all at once or can you switch between them? Do you need those phases to be exact? Do you need exactly 15 degree increments or just some sweep from 0 to 180.

I can't off hand recall the features of the DCMs in the Xilinx part, but something to consider is also whether you have the clocking resources to get what you want. Typically in a single region in the FPGA, you have access to something like 8-12 regional or global clocks. So if you want all 13 phases going to some logic via the clock network - it might be tough or impossible to do. Going via general routing resources would create horrible skew and it would probably defeat the purpose of having precise phases.

I think in general you need to elaborate on what you are trying to do.

Chris