PLL and another design together

[John K]

I've designed a PLL and want to give the clock output from there to an
another design. What is the proper way to design that ???
Defining signal and give tat to the other design.. will it work ??? Or,
should I define another entity and map the ports.. Pliz show me the
way ...

 

[Andy]

In most cases, you would encapsulate your PLL in an
entity/architecture, and instantiate that entity in the target design.
The only other general choice is a concurrent procedure call (with the
procedure defined in a package referenced by the target design), which
is limited in functionality, especially wrt synthesis.

Andy


John K wrote:

I've designed a PLL and want to give the clock output from there to an
another design. What is the proper way to design that ???
Defining signal and give tat to the other design.. will it work ??? Or,
should I define another entity and map the ports.. Pliz show me the
way ...