PLL advice needed

[Michael]

Hi everybody
I need to generate ~40-50MHz clock out of 120kHz reference signal.
Exact ratio is not important.
Low jitter is very important. Reference signal jitter is very low -
~70ps (std. dev).
Any suggestions?
Thanks!
P.S.: reference signal is +/-0.5kHz (no VCXO is pullable enough). I
have been plowing through the online datasheets for two days...

 

[Tim Wescott]

Michael wrote:

Hi everybody
I need to generate ~40-50MHz clock out of 120kHz reference signal.
Exact ratio is not important.
Low jitter is very important. Reference signal jitter is very low -
~70ps (std. dev).
Any suggestions?
Thanks!
P.S.: reference signal is +/-0.5kHz (no VCXO is pullable enough). I
have been plowing through the online datasheets for two days...

Try building a VCO with a coil/capacitor tank. You should be able to
achieve that level of jitter with careful VCO design, particularly if
you limit the amount that the varactor can pull the frequency. The On
Semi MC100EL1648 is supposed to make this easy, but I've never used it.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com