G
Girish Venkataramani
Guest
Hi
I'm new to and trying to learn Verilog PLI -- specifically VPI. I have a
few questions:
1. Is there any good/standard documentation on VPI? I searched the web,
and could only find titbits.
2. Does VPI allow you to change values of registers/nets/ports? If so how?
2.(a) Is this different from the tf_ interface (where you can do this
through tf_getp() and tf_putp())?
2.(b) Do the regs/nets that I'm attempting manipulate be passed as
arguments to a user/system task (a la tf_ interface);
2.(c) If I had a handle to this register (by traversing the design
hierarchy), can I change/query the value of the register through VPI?
2.(d) I thought vpi_get_value() and vpi_put_value() were designed to
this. But, I'm apparently mistaken (since vpi_get_value only seems to
return information about the value *type*), or I'm not doing this
properly. Your comment on this will be appreciated.
3. Here's what I'm doing - I define a usertask that I call from the
$initial block of my top module. In this task, I start a separate thread
that is designed to run concurrently with the verilog simulation. I want
the verilog simulation and thread execution to interact by
sharing/manipulating values of "certain data items" in the Verilog
modules (could be registers, nets or nets connected to ports). I want to
be able to change the values held in certain registers from this thread
(using handles to regs obtained from traversing the design hierarchy).
Is this possible?
4. Any advice on this topic will be tremendously useful.
Thanks
Girish
I'm new to and trying to learn Verilog PLI -- specifically VPI. I have a
few questions:
1. Is there any good/standard documentation on VPI? I searched the web,
and could only find titbits.
2. Does VPI allow you to change values of registers/nets/ports? If so how?
2.(a) Is this different from the tf_ interface (where you can do this
through tf_getp() and tf_putp())?
2.(b) Do the regs/nets that I'm attempting manipulate be passed as
arguments to a user/system task (a la tf_ interface);
2.(c) If I had a handle to this register (by traversing the design
hierarchy), can I change/query the value of the register through VPI?
2.(d) I thought vpi_get_value() and vpi_put_value() were designed to
this. But, I'm apparently mistaken (since vpi_get_value only seems to
return information about the value *type*), or I'm not doing this
properly. Your comment on this will be appreciated.
3. Here's what I'm doing - I define a usertask that I call from the
$initial block of my top module. In this task, I start a separate thread
that is designed to run concurrently with the verilog simulation. I want
the verilog simulation and thread execution to interact by
sharing/manipulating values of "certain data items" in the Verilog
modules (could be registers, nets or nets connected to ports). I want to
be able to change the values held in certain registers from this thread
(using handles to regs obtained from traversing the design hierarchy).
Is this possible?
4. Any advice on this topic will be tremendously useful.
Thanks
Girish