PLI and FLI

[SrFPGA]

Hi,

I there any way that the PLI and FLI can be mixed into a single
shared (.so) and loaded into modelsim. Thanks in advance

S

 

[parag_paul@hotmail.com]

On Feb 28, 9:56 pm, "SrFPGA" <sarma.nedun...@gmail.com> wrote:

Hi,

I there any way that the PLI and FLI can be mixed into a single
shared (.so) and loaded into modelsim. Thanks in advance

S

Just curious
what is FLI and where is it used. Only propretary to the ModelSim ???

 

[HT-Lab]

<parag_paul@hotmail.com> wrote in message
news:1172745224.746059.259050@s48g2000cws.googlegroups.com...

On Feb 28, 9:56 pm, "SrFPGA" <sarma.nedun...@gmail.com> wrote:
Hi,

I there any way that the PLI and FLI can be mixed into a single
shared (.so) and loaded into modelsim. Thanks in advance

S



Just curious
what is FLI and where is it used. Only propretary to the ModelSim ???

Yes, FLI is the "VHDL PLI" interface and only available on Modelsim
SE/Questa.

It is easy to use, example:
http://www.ht-lab.com/howto/fli_demo/ferndemo/socket.html

Hans
www.ht-lab.com

 

[Utku Özcan]

All PLI/FLI objects are linked during elaboration time, while design
objects are language-independent at the end. But don't forget that
before the elaboration time there are codes of two separate languages.
Therefore FLI and PLI expect by definition/implementation of languages
in the tools two separate languages to be fed. If you want to combine
FLI/PLI, then you have to combine the input languages too. This is by
definition of languages not possible, and it is IMHO a reasonably
expected simulator implementation.

There might be such language implementations in which you can mix both
languages before elaboration time, ie. you might be able to call a
VHDL procedure directly from a Verilog block, in which it might be
possible to have what you want. I don't think such tools exist.

Check out the elaboration options. PLI and FLI shared objects might be
elaborated with separate options during elaboration time. You can
decrease the number of shared objects down to 2, ie. one of each
belong to the other language. This should not be annoying. To reduce
to a "less annoying" number of PLI/FLI objects, you need to create -if
possible- one "big" PLI registry table for Verilog and another "big"
FLI registry table for VHDL.

Just a humble thought...

Utku.

On 1 Mrz., 21:00, "HT-Lab" <han...@ht-lab.com> wrote:

parag_p...@hotmail.com> wrote in message

news:1172745224.746059.259050@s48g2000cws.googlegroups.com...

On Feb 28, 9:56 pm, "SrFPGA" <sarma.nedun...@gmail.com> wrote:
Hi,

I there any way that the PLI and FLI can be mixed into a single
shared (.so) and loaded into modelsim. Thanks in advance

S

Just curious
what is FLI and where is it used. Only propretary to the ModelSim ???

Yes, FLI is the "VHDL PLI" interface and only available on Modelsim
SE/Questa.

It is easy to use, example:http://www.ht-lab.com/howto/fli_demo/ferndemo/socket.html

Hanswww.ht-lab.com