X
Xin Xiao
Guest
I want to implement this:
entity Project1 is
Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
Input1 : in STD_LOGIC_VECTOR;
Input2: in STD_LOGIC_VECTOR;
Result: out STD_LOGIC_VECTOR);
end Project1;
I got error in STD_LOGIC_VECTOR, but I want no range in this vector. How can
i do this?
Xiao Xin
entity Project1 is
Port ( Code: in STD_LOGIC_VECTOR (2 downto 0);
Input1 : in STD_LOGIC_VECTOR;
Input2: in STD_LOGIC_VECTOR;
Result: out STD_LOGIC_VECTOR);
end Project1;
I got error in STD_LOGIC_VECTOR, but I want no range in this vector. How can
i do this?
Xiao Xin