please tell me why this inout port assignment isnt working!!

[mw3382]

ok i have found the problem - i was not tristating the test module end of
the bus! i am almost certain i have set all bus connections to
16'bzzzzzzzzzzzzzzzz, but what i am seeing now on the simulation is the
value 000000000000000z. is this a common error?

 

[mw3382]

sorry that was wrong it was 16'bzzzzzzzzzzzzzzzz not 16'b1010101010101010

 

[mw3382]

Hi,

I am implementing a simple cache memory system with an inout data bus
(cpu_data), and I have this line of code

assign cpu_data = (mem_to_cpu) ? temp : ((cache_to_cpu) ? cachemem[index]:
16'b1010101010101010);

The simulation shows that mem_to_cpu is always 0 and cache_to_cpu changes
from 0 to 1, but cpu_data remains at xxxxxxxxxxxxxxxx throughout the
simulation. I am not assigning any other values to cpu_data. Any ideas?

Thanks,
Mike

 

[Mike Lewis]

Well you don't really have an inout bus ... cpu_data is always
driving and never goes tri-state.

cpu_data can be "x" if there is something else driving the data bus.
Do you have another entity in your simulation that can drive cpu_data?

Mike

"mw3382" <mike_wrighton@hotmail.com> wrote in message
news:ea60afe129786b754c5098d20261f9d9@localhost.talkaboutprogramming.com...

Hi,

I am implementing a simple cache memory system with an inout data bus
(cpu_data), and I have this line of code

assign cpu_data = (mem_to_cpu) ? temp : ((cache_to_cpu) ? cachemem[index]:
16'b1010101010101010);

The simulation shows that mem_to_cpu is always 0 and cache_to_cpu changes
from 0 to 1, but cpu_data remains at xxxxxxxxxxxxxxxx throughout the
simulation. I am not assigning any other values to cpu_data. Any ideas?

Thanks,
Mike