Please take a look of my double sided PCB layout and critici

V

vax, 9000

Guest
Hi, list,
I am designing a homebrew double sided PCB. My only experience were from
DOS TANGO years ago. The board is half done and any recommendations are
welcome. I don't want to know that I am making serious mistakes when the
board is done.
I am using 9mil traces for signals some will carry 70mA current (when
drive the edge connectors low). Vias for signal have diameter of 36mil with
20mil holes. Vias for power lines have diameter of 45mil with 29mil holes.
Power and GND trace width is 40mil (25mil if there is no space). Power
current mostly goes to the SCSI terminators, I guess. That would be several
hundred mA.
Files are in postscript format.
http://geocities.com/mscpscsi/PHOTOS/front.ps
http://geocities.com/mscpscsi/PHOTOS/back.ps
http://geocities.com/mscpscsi/PHOTOS/silk.ps

Thank you.
vax, 9000
 
I am designing a homebrew double sided PCB. My only experience were from
DOS TANGO years ago. The board is half done and any recommendations are
welcome. I don't want to know that I am making serious mistakes when the
board is done.
Click to expand...
What sort of clock speeds and/or edge rates are you using?

Do you need a ground plane?

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
Boris Mohar wrote:
You will get better response if you post Gerber files.
Click to expand...
Or still better PDFs. If the program can output to Windows printers, you
can download PDF Creator from <http://sourceforge.net/projects/pdfcreator/>

Paul Burke
 
Paul Burke wrote:

Boris Mohar wrote:


You will get better response if you post Gerber files.

Or still better PDFs. If the program can output to Windows printers, you
can download PDF Creator from
http://sourceforge.net/projects/pdfcreator/
Click to expand...
Thank you. I have just uploaded Gerber files.

I used "ps2pdf" in Redhat to generate .pdf files. However, it changes the
vector graphics into .ps file into pixel based graphics. I didn't post the
..pdf files because of this problem.

Have a nice day
vax, 9000

Paul Burke
Click to expand...
 
On Sun, 13 Feb 2005 23:23:26 -0500, "vax, 9000" <vax9000@gmail.com> wrote:

Hi, list,
I am designing a homebrew double sided PCB. My only experience were from
DOS TANGO years ago. The board is half done and any recommendations are
welcome. I don't want to know that I am making serious mistakes when the
board is done.
I am using 9mil traces for signals some will carry 70mA current (when
drive the edge connectors low). Vias for signal have diameter of 36mil with
20mil holes. Vias for power lines have diameter of 45mil with 29mil holes.
Power and GND trace width is 40mil (25mil if there is no space). Power
current mostly goes to the SCSI terminators, I guess. That would be several
hundred mA.
Files are in postscript format.
http://geocities.com/mscpscsi/PHOTOS/front.ps
http://geocities.com/mscpscsi/PHOTOS/back.ps
http://geocities.com/mscpscsi/PHOTOS/silk.ps

Thank you.
vax, 9000
Click to expand...
You will get better response if you post Gerber files.




Regards,

Boris Mohar

Got Knock? - see:
Viatrack Printed Circuit Designs (among other things) http://www.viatrack.ca
 
Hal Murray wrote:

I am designing a homebrew double sided PCB. My only experience were from
DOS TANGO years ago. The board is half done and any recommendations are
welcome. I don't want to know that I am making serious mistakes when the
board is done.

What sort of clock speeds and/or edge rates are you using?
Click to expand...
The clock is 20MHz. The DIP 20pin chips are 74LSXXX, the CPU is 80C188XL.
Other big chips (EPROM, SRAM, SCSI controller, UART controller) are all
slow. Their edge rates are mostly from 5ns to 10ns, or longer. The two
small chips are 74alvt16244/16245, their edge rates are faster, maybe
around 2 ns. The blank place will have a Altera EPM1270, whose edge rate
can be programmed to be several ns.

gerber files are uploaded to

http://wintersweet.com/permenent/front.gbr
http://wintersweet.com/permenent/back.gbr
http://wintersweet.com/permenent/silk.gbr

vax, 9000

Do you need a ground plane?
Click to expand...
 
Boris Mohar wrote:

On Sun, 13 Feb 2005 23:23:26 -0500, "vax, 9000" <vax9000@gmail.com> wrote:

Hi, list,
I am designing a homebrew double sided PCB. My only experience were from
DOS TANGO years ago. The board is half done and any recommendations are
welcome. I don't want to know that I am making serious mistakes when the
board is done.
I am using 9mil traces for signals some will carry 70mA current (when
drive the edge connectors low). Vias for signal have diameter of 36mil
with 20mil holes. Vias for power lines have diameter of 45mil with 29mil
holes. Power and GND trace width is 40mil (25mil if there is no space).
Power current mostly goes to the SCSI terminators, I guess. That would be
several hundred mA.
Files are in postscript format.
http://geocities.com/mscpscsi/PHOTOS/front.ps
http://geocities.com/mscpscsi/PHOTOS/back.ps
http://geocities.com/mscpscsi/PHOTOS/silk.ps

Thank you.
vax, 9000

You will get better response if you post Gerber files.
Click to expand...
Gerber files are uploaded. Please refer to my Re to Hal's post. I need help
from you guys who have experience. Thanks.

vax, 9000

Regards,

Boris Mohar

Got Knock? - see:
Viatrack Printed Circuit Designs (among other things)
http://www.viatrack.ca
Click to expand...
 
vax, 9000 <vax9000@gmail.com> wrote:
: Hal Murray wrote:

:>> I am designing a homebrew double sided PCB. My only experience were from
:>>DOS TANGO years ago. The board is half done and any recommendations are
:>>welcome. I don't want to know that I am making serious mistakes when the
:>>board is done.
:>
:> What sort of clock speeds and/or edge rates are you using?

: The clock is 20MHz. The DIP 20pin chips are 74LSXXX, the CPU is 80C188XL.
: Other big chips (EPROM, SRAM, SCSI controller, UART controller) are all
: slow. Their edge rates are mostly from 5ns to 10ns, or longer. The two
: small chips are 74alvt16244/16245, their edge rates are faster, maybe
: around 2 ns. The blank place will have a Altera EPM1270, whose edge rate
: can be programmed to be several ns.

I think you should do (at least) a 4 layer board, with this stackup:

Sig (Vertical)
GND
VCC
Sig (Horizontal)

This will help you for a couple of reasons:

* You are going to run out of routing space soon, given that you've
got so many multi-pin components. Going to four layers will help a
lot.

* Your rise times are not slow, at least your power distribution
network. As you have it now, each VCC track is a big, long inductor,
and you might couple glitches from one device to the next, or from VCC
to a signal net via crosstalk. Use Power and GND planes to aviod this
problem.

* Also, your current PDS (power distribution system) will radiate a
lot since both your VCC and GND are just long antennas. Having a GND
plane will help a lot.

* I don't recall seeing decoupling caps. Place one ceramic 0.1uF cap
at the top of each DIP, and several around your BGAs. In fact, you
can profitably throw the caps inside the middle openings of the BGAs,
on the board's back side. Also, scatter
some 4.7uF tantalum caps around your board for bulk decoupling.
Again, this technique requires a power and GND plane in order to
work. (If you did have decoupling caps which I didn't notice, then
carry on as usual . . . . .)

I believe you are using gEDA/PCB, right? You can do up to 6 layers
with PCB; the only reason not to is cost, whcih isn't that much
compared to the price of an FPGA. And 4 layers is certainly cheap
compared to a respin necessitated by signal integrity problems on your
PDS.

Stuart
 
"vax, 9000" <vax9000@gmail.com> wrote in message
news:cuqg9r$3g8$1@charm.magnus.acs.ohio-state.edu...
Hal Murray wrote:

I am designing a homebrew double sided PCB. My only experience were
from
DOS TANGO years ago. The board is half done and any recommendations are
welcome. I don't want to know that I am making serious mistakes when the
board is done.

What sort of clock speeds and/or edge rates are you using?

The clock is 20MHz. The DIP 20pin chips are 74LSXXX, the CPU is 80C188XL.
Other big chips (EPROM, SRAM, SCSI controller, UART controller) are all
slow. Their edge rates are mostly from 5ns to 10ns, or longer. The two
small chips are 74alvt16244/16245, their edge rates are faster, maybe
around 2 ns. The blank place will have a Altera EPM1270, whose edge rate
can be programmed to be several ns.
Click to expand...
Those parts are rather ancient, no-one designs anything like that these
days.

Leon
 
On Mon, 14 Feb 2005 10:38:57 -0500, "vax, 9000" <vax9000@gmail.com> wrote:




Gerber files are uploaded. Please refer to my Re to Hal's post. I need help
from you guys who have experience. Thanks.

vax, 9000


I just glanced at it so don't hold me up to it.
Click to expand...

1. Generous amount of power supply decoupling capacitors would be more than
useful.

2. front.gbr has few rather large loops. Break them because they are
susceptible to radiation and picking up radiation. You are almost there.
Just run the power bus across the top and drop parallel power and ground in
few places. No need for redundancy at the bottom.

3. Clean up the silk screen

4 If you can afford it go for four layers.



Regards,

Boris Mohar

Got Knock? - see:
Viatrack Printed Circuit Designs (among other things) http://www.viatrack.ca
 
Boris Mohar wrote:

I just glanced at it so don't hold me up to it.

1. Generous amount of power supply decoupling capacitors would be more
than useful.

2. front.gbr has few rather large loops. Break them because they are
susceptible to radiation and picking up radiation. You are almost there.
Just run the power bus across the top and drop parallel power and ground
in
few places. No need for redundancy at the bottom.

3. Clean up the silk screen

4 If you can afford it go for four layers.
Click to expand...
Thank you and all others who have responded. I forgot to add decoupling
capacitors entirely. I will also drop the power traces parallel to the
ground traces. I plan to redo some of the work, and run ground traces
vertically on the bottom layer, power lines horizontally on the top layer,
and add decoupling capacitors at places where they meet. I will use the
bottom layer as ground panel under the faster surface mount IC's. I will
also pretect the clock main trace with ground around it (Now it is between
the parallel power and ground traces).

I will stay with double sided board for now and consider 4 layers in the
future for other projects. This board is designed with old stuff because it
interfaces with old Q22 bus and 8 bit SCSI-2 disks.

I am using gEDA/PCB. There are some bugs but I managed to work around them
and so far it works great.

regards,
vax, 9000


Regards,

Boris Mohar

Got Knock? - see:
Viatrack Printed Circuit Designs (among other things)
http://www.viatrack.ca
Click to expand...
 
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