please let me know what hardware is generated for this piece

[a]

module latch(v1,v2,v3,c1,c2);
input v1,v2,v3,c1,c2;
//output b;
reg a,b;
always @ (*)
begin
a=v1;
if (c1) b=a|v2;
if(c2) b=v3;
end
endmodule

 

[a]

i understand incomplete if statements generate latches
but isnt there a conflict here as both the latches are trying to write
to b
wat happens

 

[m]

On 2 Feb 2006 23:48:55 -0800, "a" <a@tempinbox.com> wrote:

i understand incomplete if statements generate latches
but isnt there a conflict here as both the latches are trying to write
to b
wat happens

There is no conflict. Blocking assignments (within a single always
block) are executed in order so if c2 is true it overrides the value
of b (possibly assigned by c1 previously) otherwise if c1 is true it
overrides the value of b otherwise the previous value of b is
remembered. So last writer wins or c2 has priority when both c1 and c2
are true.

 

[Chris F Clark]

Since this looks like a homework problem, the snide answer is
potentially nothing as the module has no outputs. However, a more
sensible answer is a latch with a gated clock driven by a mux. I'll
leave it to you to figure out which inputs get connected to the latch
and which to the mux. Why would you have such a piece of logic,
especially if it is poorly documented and with such descriptive names?

-Chris

 

[a]

thanks
mk wrote:

On 2 Feb 2006 23:48:55 -0800, "a" <a@tempinbox.com> wrote:

i understand incomplete if statements generate latches
but isnt there a conflict here as both the latches are trying to write
to b
wat happens

There is no conflict. Blocking assignments (within a single always
block) are executed in order so if c2 is true it overrides the value
of b (possibly assigned by c1 previously) otherwise if c1 is true it
overrides the value of b otherwise the previous value of b is
remembered. So last writer wins or c2 has priority when both c1 and c2
are true.

 

[a]

thanks
mk wrote:

On 2 Feb 2006 23:48:55 -0800, "a" <a@tempinbox.com> wrote:

i understand incomplete if statements generate latches
but isnt there a conflict here as both the latches are trying to write
to b
wat happens

There is no conflict. Blocking assignments (within a single always
block) are executed in order so if c2 is true it overrides the value
of b (possibly assigned by c1 previously) otherwise if c1 is true it
overrides the value of b otherwise the previous value of b is
remembered. So last writer wins or c2 has priority when both c1 and c2
are true.

 

[GEO]

a wrote:

module latch(v1,v2,v3,c1,c2);
input v1,v2,v3,c1,c2;
//output b;
reg a,b;
always @ (*)
begin
a=v1;
if (c1) b=a|v2;
if(c2) b=v3;
end
endmodule

I just ran a similar code through ise 8.1i, and here is the funny
observation:

ISE 8.1i:

I took this one through ise:

.. `timescale 1ns / 1ps
.. module latch(a,b, c,d,e);
.. input a,b;
.. output c,d,e;
.. reg c,d,e;
.. always @(*)
.. // always @(a or b )
.. begin
.. if ( a ) begin
.. c = a;
.. e = a;
.. end
.. if ( b ) begin
.. d = b;
.. e = b;
.. end
..
.. end
.. endmodule


For C, it puts a LD with D tied to VCC, gate tied to A
For D, it puts a LD with D tied to VCC, gate tied to B ( only
connection for B)
for E, it puts a LDP with Aset floting ( according to schematic)
D tied to VCC, and gate tied to A


Any comments Xilinx experts ?

Thanks in advance!