Please Help

[Samiran]

Dear all,

I am trying to instantiate a verilog-A module (e.g. module-1) inside
another verilog-A code (e.g. module-2). I know that if module-1 is
defined in the same verilog-A file the I can instantiate using the
following syntax:

module-1 #(.var(var_value)) INSTANCE_NAME(port#1, port#2,...);

But, if Module-1 is defined in a separate verilog-A file, how I can
implement this?

Regards,
Samiran

 

[Rick Mattern]

On Apr 4, 8:13 am, Samiran <samiran....@gmail.com> wrote:

Dear all,

I am trying to instantiate a verilog-A module (e.g. module-1) inside
another verilog-A code (e.g. module-2). I know that if module-1 is
defined in the same verilog-A file the I can instantiate using the
following syntax:

module-1 #(.var(var_value)) INSTANCE_NAME(port#1, port#2,...);

But, if Module-1 is defined in a separate verilog-A file, how I can
implement this?

Regards,
Samiran

There is no difference between a block that is defined locally or
externally,
both require a module statement which defines the block and a
instantition
line providing that they are both subcells.

The instantition sytax is:

<blockName> <instanceName> (
.<pinName>(<netName&gt,
.<pinName>(<netName&gt,
);

Rick