Please help with bidirectional data bus code..........

[Agreychu]

Hello,i am new to Verilog HDL.i have a module with a inout signal.But
i don't know what problem to my verilog code.

I want to write a module like this:


<----->DATA |
------>ADDR |
------>WR |
------>RD |
------>RESET|

DATA is an inout signal,controled by WR or RD(Write enable or Read
enable).ADDR is address.
Here is my verilog code:

module mem(ADDR,DATA,RD,WR,RESET);

input [7:0] ADDR;
inout [7:0] DATA;
tri [7:0] DATA;
input RESET;
input WR;
input RD;

reg [7:0] b[0:255];
reg [7:0] a;

assign DATA = (WR)? a : 8'bz ;

always @ (posedge WR or RD or RESET)
begin
if (!RESET)
a<=8'bz;
else if(RD)
b[ADDR]<=DATA;
else if(WR)
a <= b[ADDR];
else
a<=8'bz;
end
endmodule

But simulation result was wrong.Please tell me how should I fix it,or
another method to implement bidirectional data,thx.

Have a nice day.

 

[Neo]

Hi,
you are writing with 'rd' signal and reading with 'wr' signal.
also you should not actually have edge and level triggers in one
sensitivity list.
You dont have the 'data' in the sentivity list and also your reset
inclusion in the list is also a suspect(why do you need that) anyway
you get latch with that included. with these corrections it should
work.

 

[Neo]

Also, you have to include the address inthe sensitivity list.

 

[Agreychu]

Thx, i really got misunderstanding the 'read' and 'write'......

so i fix it as below structure :

______________________________________________
DATA BUS
_______________________________________________
| ^
| |
| |
| ________ |
| | | |\ |
|--->| |________| \___________|
| | | /
| | |/o
WR ----|> | |
|______| |
| RD_____|
|
RESET_____|

and the verilog code is :
module mem(ADDR,DATA,RD,WR,RESET);

input [7:0] ADDR;
inout [7:0] DATA;
tri [7:0] DATA;
input RESET;
input WR;
input RD;
reg [7:0] b[0:10];

assign DATA=(!RD)?b[ADDR]:8'hzz;

always @ (posedge WR or RESET)
begin
if (!RESET)
b[ADDR] <= 8'hzz;
else if (WR)
b[ADDR] <= DATA ;
end
endmodule

is that right code?
thx again. ^^

 

[Neo]

yeah somewhat, but you are using the write signal like a clock. is that
what you want? and under reset you are assigning "zz" which wont
synthesize as such. you can assign zeros for proper systhesis.
But again if the above diagram is what you want then its ok except for
assigning "zz" but if you are modelling memory then you have to remove
that edge trigger and make the palways block combinational logic by
making the sentivity list as: @(wr or data) and remove reset signal.

 

[Agreychu]

thanks, i had correct the "zz" to zero,and that diagram is what i
want.^^
But i got confused between my diagram and the memory module Neo
mentioned.

Neo say that :
"you have to remove that edge trigger and make the palways block
combinational logic by making the sentivity list as: @(wr or data) and
remove reset signal."

I don't understand what that exactly meaning.Could u explain more to
me??

THx again and have a nice day. ^^

 

[Jonathan Bromley]

On 30 Jan 2005 19:19:50 -0800, s918401@mail.yzu.edu.tw (Agreychu)
wrote:

Hello,i am new to Verilog HDL.i have a module with a inout signal.But
i don't know what problem to my verilog code.

I want to write a module like this:

I think you are misunderstanding the idea of "read" and "write".
The module you are creating is a memory. For a memory, "write"
usually means "data comes into the memory from the outside"
and "read" usually means "data goes from the memory to the
outside". You have exchanged these two ideas.

Have a nice day.

You too.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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are not the views of Doulos Ltd., unless specifically stated.

 

[MysticSage]

Normally in industry, logic is designed as synchronous logic and there
is one more signal behaving like "clock". Since clock signal is
present, WR is normally used in combinatorial logic.

That set aside, "WR" is being is used as clock signal in your case
which may have confused "neo". But there is nothing wrong if it is
speciality code. Following is my take on your code.

always @ (posedge WR or RESET)

Industry "synthesis" tools do not support this. It should be
always @ (posedge WR or negedge RESET) --> implemented as FLIP-FLOP

begin
if (!RESET)
b[ADDR] <= 8'hzz;

At reset, ADDR value is unknown. So which ADDR??? Also do you want it
to be Flip-Flop based array/memory structure? if yes, then all flops
should be assigned a known value. "Z" is not known value for FLOPS. It
may work in simulation but synthesis result may not be predictable.

More appropriate may be
if (!RESET)
for (i=0; i < 256; i=i+1) b <= 8'h00; // Known values assigned to
all flops

else if (WR)
b[ADDR] <= DATA ;
end

Have fun,