please help! state machine

S

Simone Winkler

Guest
Hello!

I've got a strange problem that I don't know any solution for - up to now I
tried everything, but it didn't work.
The state machine always stops to go to the next state - I
really don't understand why.

I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA,
VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains in
the WRITE_INIT state all the time. WHY????
The 2nd (smaller) problem is, that the data at write_out comes one clock
cycle too late. I understand why, but how can i change this?

I don't know if it's a good idea to solve my problem with my kind of code,
i'm an "advanced beginner" and as I am used to program "sequential
programming languages" I've got big problems with doing sequential things in
vhdl. What is the easy way to do things one after the other, e.g. write one
byte after the other? (also to be synthesizable).

I put the code at http://members.liwest.at/simsi/stuff/usb.vhd, because it's
quite long to put it here. (don't be afraid - no virus!)

Please help me! I really don't know where to go on.

Thank you,
Simone
 
What program you using ..Quartus?

"Simone Winkler" <simone.winkler@gmx.at> wrote in message
news:1073153426.69428@news.liwest.at...
Hello!

I've got a strange problem that I don't know any solution for - up to now
I
tried everything, but it didn't work.
The state machine always stops to go to the next state - I
really don't understand why.

I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA,
VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains
in
the WRITE_INIT state all the time. WHY????
The 2nd (smaller) problem is, that the data at write_out comes one clock
cycle too late. I understand why, but how can i change this?

I don't know if it's a good idea to solve my problem with my kind of code,
i'm an "advanced beginner" and as I am used to program "sequential
programming languages" I've got big problems with doing sequential things
in
vhdl. What is the easy way to do things one after the other, e.g. write
one
byte after the other? (also to be synthesizable).

I put the code at http://members.liwest.at/simsi/stuff/usb.vhd, because
it's
quite long to put it here. (don't be afraid - no virus!)

Please help me! I really don't know where to go on.

Thank you,
Simone
Click to expand...
 
: What program you using ..Quartus?

Xilinx ISE Webpack 5.2i with ServicePack, Modelsim XE 5.6e Starter.
 
Simone Winkler wrote:
Hello!

I've got a strange problem that I don't know any solution for - up to now I
tried everything, but it didn't work.
The state machine always stops to go to the next state - I
really don't understand why.

I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA,
VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains in
the WRITE_INIT state all the time. WHY????
The 2nd (smaller) problem is, that the data at write_out comes one clock
cycle too late. I understand why, but how can i change this?

I don't know if it's a good idea to solve my problem with my kind of code,
i'm an "advanced beginner" and as I am used to program "sequential
programming languages" I've got big problems with doing sequential things in
vhdl. What is the easy way to do things one after the other, e.g. write one
byte after the other? (also to be synthesizable).

I put the code at http://members.liwest.at/simsi/stuff/usb.vhd, because it's
quite long to put it here. (don't be afraid - no virus!)

Please help me! I really don't know where to go on.
Click to expand...
And later posted:

Xilinx ISE Webpack 5.2i with ServicePack, Modelsim XE 5.6e Starter.
Click to expand...
You should be able to use Modelsim to duplicate the lockup, and
therefore see what input to the state machine is causing you the problem.

BTW, you may not be getting what you expect with at least one of your
procedures since the clocked part of the procedure is within another if
statement.

Also, the proper newsgroup for this type of question is

news:comp.lang.vhdl

Have fun,

Marc
 
For starters make sure that your sensitivity list is complete. It isn't at
present and some simulators will simply ignore statements where the "input"
signals are not in the sensitivity list. Synthesisers should do something
similar in theory but most "assume" the sensitivity list.

John Adair
Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.


"Simone Winkler" <simone.winkler@gmx.at> wrote in message
news:1073153426.69428@news.liwest.at...
Hello!

I've got a strange problem that I don't know any solution for - up to now
I
tried everything, but it didn't work.
The state machine always stops to go to the next state - I
really don't understand why.

I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA,
VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains
in
the WRITE_INIT state all the time. WHY????
The 2nd (smaller) problem is, that the data at write_out comes one clock
cycle too late. I understand why, but how can i change this?

I don't know if it's a good idea to solve my problem with my kind of code,
i'm an "advanced beginner" and as I am used to program "sequential
programming languages" I've got big problems with doing sequential things
in
vhdl. What is the easy way to do things one after the other, e.g. write
one
byte after the other? (also to be synthesizable).

I put the code at http://members.liwest.at/simsi/stuff/usb.vhd, because
it's
quite long to put it here. (don't be afraid - no virus!)

Please help me! I really don't know where to go on.

Thank you,
Simone
Click to expand...
 
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