please help! modelsim error

[Arnaud Douville]

The use of pragmas will not resolve your problem at all.

Apparently we want to simulate in the library work the entity
testbench (work.testbench). The problem is that in the code you
attached I could not see an entity called testbench!!!

Maybe your project navigator is not properly configured if it launches
automatically ModelSim, so try the following:
In ModelSim, click on:
Simulate -----> Simulate
Then choose your entity in the list:
work ------> fifo_c_tb
Then click on Load button


"Simone Winkler" <simone.winkler@gmx.at> wrote in message news:<1066717657.980407@news.liwest.at>...

Hello!

I'm trying to simulate a FIFO design for a Xilinx Spartan2-FPGA in Modelsim.
The code for the FIFO is taken from the application notes on the Xilinx
homepage.
I'm working with ISE Webpack 5.1i and Modelsim XE Starter 5.6e.

Every time i try to simulate (I do this out of the project navigator which
automatically launches modelsim), it tells me the following thing:

# ** Error: (vsim-3173) Entity 'work.testbench' has no architecture.

The code for my testbench looks like this:
_____________________________________________

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity fifo_c_tb is
end fifo_c_tb;

architecture test of fifo_c_tb is
component fifoctlr_cc
port (clock_in: in std_ulogic;
read_enable_in: in std_ulogic;
write_enable_in: in std_ulogic;
write_data_in: in std_ulogic_vector(15 downto 0);
fifo_gsr_in: in std_ulogic;
read_data_out: out std_ulogic_vector(15 downto 0);
full_out: out std_ulogic;
empty_out: out std_ulogic;
fifocount_out: out std_ulogic_vector(7 downto 0));
end component;

constant clk_delay_c : time := 50 ns;

signal clock_s: std_ulogic;
signal read_enable_s: std_ulogic;
signal write_enable_s: std_ulogic;
signal write_data_s: std_ulogic_vector(15 downto 0);
signal fifo_gsr_s: std_ulogic;
signal read_data_s: std_ulogic_vector(15 downto 0);
signal full_s: std_ulogic;
signal empty_s: std_ulogic;
signal fifocount_s: std_ulogic_vector(7 downto 0);

begin
u1: fifoctlr_cc
port map(
clock_in => clock_s,
read_enable_in => read_enable_s,
write_enable_in => write_enable_s,
write_data_in => write_data_s,
fifo_gsr_in => fifo_gsr_s,
read_data_out => read_data_s,
full_out => full_s,
empty_out => empty_s,
fifocount_out => fifocount_s
);


-- *** Test Bench - User Defined Section ***
clock: process
begin
[...]
_______________________________________________


Do you know what the problem is? I heard about inserting pragmas to exclude
unisim librarys, but it didn't really work (probably because i didn't really
know if i do the right thing...)
I'm not very familiar with modelsim yet - so can you please help me??

Thank you!

Simone