please help! modelsim error

[Simone Winkler]

Hello!

I'm trying to simulate a FIFO design for a Xilinx Spartan2-FPGA in Modelsim.
The code for the FIFO is taken from the application notes on the Xilinx
homepage.
I'm working with ISE Webpack 5.1i and Modelsim XE Starter 5.6e.

Every time i try to simulate (I do this out of the project navigator which
automatically launches modelsim), it tells me the following thing:

# ** Error: (vsim-3173) Entity 'work.testbench' has no architecture.

The code for my testbench looks like this:
_____________________________________________

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity fifo_c_tb is
end fifo_c_tb;

architecture test of fifo_c_tb is
component fifoctlr_cc
port (clock_in: in std_ulogic;
read_enable_in: in std_ulogic;
write_enable_in: in std_ulogic;
write_data_in: in std_ulogic_vector(15 downto 0);
fifo_gsr_in: in std_ulogic;
read_data_out: out std_ulogic_vector(15 downto 0);
full_out: out std_ulogic;
empty_out: out std_ulogic;
fifocount_out: out std_ulogic_vector(7 downto 0));
end component;

constant clk_delay_c : time := 50 ns;

signal clock_s: std_ulogic;
signal read_enable_s: std_ulogic;
signal write_enable_s: std_ulogic;
signal write_data_s: std_ulogic_vector(15 downto 0);
signal fifo_gsr_s: std_ulogic;
signal read_data_s: std_ulogic_vector(15 downto 0);
signal full_s: std_ulogic;
signal empty_s: std_ulogic;
signal fifocount_s: std_ulogic_vector(7 downto 0);

begin
u1: fifoctlr_cc
port map(
clock_in => clock_s,
read_enable_in => read_enable_s,
write_enable_in => write_enable_s,
write_data_in => write_data_s,
fifo_gsr_in => fifo_gsr_s,
read_data_out => read_data_s,
full_out => full_s,
empty_out => empty_s,
fifocount_out => fifocount_s
);


-- *** Test Bench - User Defined Section ***
clock: process
begin
[...]
_______________________________________________


Do you know what the problem is? I heard about inserting pragmas to exclude
unisim librarys, but it didn't really work (probably because i didn't really
know if i do the right thing...)
I'm not very familiar with modelsim yet - so can you please help me??

Thank you!

Simone

 

[Renaud Pacalet]

Simone Winkler a écrit :

Hello!

I'm trying to simulate a FIFO design for a Xilinx Spartan2-FPGA in Modelsim.
The code for the FIFO is taken from the application notes on the Xilinx
homepage.
I'm working with ISE Webpack 5.1i and Modelsim XE Starter 5.6e.

Every time i try to simulate (I do this out of the project navigator which
automatically launches modelsim), it tells me the following thing:

# ** Error: (vsim-3173) Entity 'work.testbench' has no architecture.

The code for my testbench looks like this:
...
entity fifo_c_tb is
end fifo_c_tb;
...
Do you know what the problem is?

As your entity is named fifo_c_tb did you try to simulate work.fifo_c_tb instead
of work.testbench?

Regards,
--
Renaud Pacalet, GET/ENST/COMELEC/LabSoC
Institut Eurecom BP 193, 2229 route des Cretes
F-06904 Sophia-Antipolis Cedex
Tel : +33 (0) 4 9300 2770
Fax : +33 (0) 4 9300 2627
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