please help, modelsim does not simulate

S

Simone Winkler

Guest
Hello!

I'm performing a VHDL design for a Xilinx Spartan2-FPGA that implements a
synchronous FIFO.
Actually, at the moment, I'm just using the Application Note Design offered
on the Xilinx Wepage (XAPP175).
So far, so good, I've got a testbench to be run in Modelsim.
But every time it tells me the following things:

___________________________________________________________________

# Reading D:/Programme/Modeltech_xe/tcl/vsim/pref.tcl
# do fifo_c_tb.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fifoctlr_cc
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture fifoctlr_cc_hdl of fifoctlr_cc
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity fifoctlr_cc
# WARNING[1]: fifo_c.vhd(97): No default binding for component: "bufgp". (No
entity named "bufgp" was found)
# WARNING[1]: fifo_c.vhd(110): No default binding for component:
"ramb4_s8_s8". (No entity named "ramb4_s8_s8" was found)
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fifo_c_tb
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture test of fifo_c_tb
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity fifo_c_tb
# -- Loading entity fifoctlr_cc
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port write_data_in
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port read_data_out
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port fifocount_out
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# vsim -L xilinxcorelib -lib work -t 1ps testbench
# ** Warning: A ModelSim starter license was detected and will be used, even
though you have installed ModelSim XE. You should obtain an XE license in
order to access ModelSim XE's full capabilities.# Loading
D:/Programme/Modeltech_xe/win32xoem/../std.standard
# ** Error: (vsim-3173) Entity 'work.testbench' has no architecture.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./fifo_c_tb.fdo PAUSED at line 9
__________________________________________________________________


The two components RAMB4_S1 and BUFGP should be in a library - so i don't
understand why it's not found.
I don't understand, why the ports don't match - they are really the same
type (most of them std_ulogic(_vector)).
And at the end, why does it say "Entity 'work.testbench' has no
architecture" ?
My idea is that i need a configuration file. But i'm doing everything out of
Xilinx ISE Webpack, there i never need a configuration file, or do i? I'm
quite out of understanding at the moment...:(.



My TestBench-Code (at least parts of it) was:
___________________________________________

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;

entity fifo_c_tb is
end fifo_c_tb;

architecture test of fifo_c_tb is
component fifoctlr_cc
port (clock_in: in std_ulogic;
read_enable_in: in std_ulogic;
write_enable_in: in std_ulogic;
write_data_in: in std_ulogic_vector(15 downto 0);
fifo_gsr_in: in std_ulogic;
read_data_out: out std_ulogic_vector(15 downto 0);
full_out: out std_ulogic;
empty_out: out std_ulogic;
fifocount_out: out std_ulogic_vector(7 downto 0));
end component;

constant clk_delay_c : time := 50 ns;

signal clock_s: std_ulogic;
signal read_enable_s: std_ulogic;
signal write_enable_s: std_ulogic;
signal write_data_s: std_ulogic_vector(15 downto 0);
signal fifo_gsr_s: std_ulogic;
signal read_data_s: std_ulogic_vector(15 downto 0);
signal full_s: std_ulogic;
signal empty_s: std_ulogic;
signal fifocount_s: std_ulogic_vector(7 downto 0);

begin
u1: fifoctlr_cc
port map(
clock_in => clock_s,
read_enable_in => read_enable_s,
write_enable_in => write_enable_s,
write_data_in => write_data_s,
fifo_gsr_in => fifo_gsr_s,
read_data_out => read_data_s,
full_out => full_s,
empty_out => empty_s,
fifocount_out => fifocount_s
);


-- *** Test Bench - User Defined Section ***
clock: process
begin
[...]
__________________________________________________

please help me!!

Thank you, Simone

-------------------------------------------------------------------
Simone Winkler
Mechatronik-Studentin / Universität Linz
simone.winkler@students.jku.at
ICQ: 20212150
 
This happens because Modelsim is not finding the appropriate library
declaring bufg...

at the top of your vhdl file when you include the libraries add
something like

-- synopsys translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synopsys translate_on


Garry Allen
not that i have ever been tricked by this problem in the past. No not
at all
 
Couple of things:

1) This question belongs in comp.lang.vhdl, probably.
2) Find the Xilinx primitives (deep in your xilinx directory) and
include them in the simulation file list.

ModelSim is probably so upset about not finding them (missing RAM
makes for a poor FIFO) that it's dumping the whole thing.

HTH,
SH


"Simone Winkler" <simone.winkler@gmx.at> wrote in message news:<1066686601.590067@news.liwest.at>...
Hello!

I'm performing a VHDL design for a Xilinx Spartan2-FPGA that implements a
synchronous FIFO.
Actually, at the moment, I'm just using the Application Note Design offered
on the Xilinx Wepage (XAPP175).
So far, so good, I've got a testbench to be run in Modelsim.
But every time it tells me the following things:

___________________________________________________________________

# Reading D:/Programme/Modeltech_xe/tcl/vsim/pref.tcl
# do fifo_c_tb.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fifoctlr_cc
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture fifoctlr_cc_hdl of fifoctlr_cc
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity fifoctlr_cc
# WARNING[1]: fifo_c.vhd(97): No default binding for component: "bufgp". (No
entity named "bufgp" was found)
# WARNING[1]: fifo_c.vhd(110): No default binding for component:
"ramb4_s8_s8". (No entity named "ramb4_s8_s8" was found)
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fifo_c_tb
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture test of fifo_c_tb
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity fifo_c_tb
# -- Loading entity fifoctlr_cc
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port write_data_in
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port read_data_out
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port fifocount_out
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# vsim -L xilinxcorelib -lib work -t 1ps testbench
# ** Warning: A ModelSim starter license was detected and will be used, even
though you have installed ModelSim XE. You should obtain an XE license in
order to access ModelSim XE's full capabilities.# Loading
D:/Programme/Modeltech_xe/win32xoem/../std.standard
# ** Error: (vsim-3173) Entity 'work.testbench' has no architecture.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./fifo_c_tb.fdo PAUSED at line 9
__________________________________________________________________


The two components RAMB4_S1 and BUFGP should be in a library - so i don't
understand why it's not found.
I don't understand, why the ports don't match - they are really the same
type (most of them std_ulogic(_vector)).
And at the end, why does it say "Entity 'work.testbench' has no
architecture" ?
My idea is that i need a configuration file. But i'm doing everything out of
Xilinx ISE Webpack, there i never need a configuration file, or do i? I'm
quite out of understanding at the moment...:(.



My TestBench-Code (at least parts of it) was:
___________________________________________

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;

entity fifo_c_tb is
end fifo_c_tb;

architecture test of fifo_c_tb is
component fifoctlr_cc
port (clock_in: in std_ulogic;
read_enable_in: in std_ulogic;
write_enable_in: in std_ulogic;
write_data_in: in std_ulogic_vector(15 downto 0);
fifo_gsr_in: in std_ulogic;
read_data_out: out std_ulogic_vector(15 downto 0);
full_out: out std_ulogic;
empty_out: out std_ulogic;
fifocount_out: out std_ulogic_vector(7 downto 0));
end component;

constant clk_delay_c : time := 50 ns;

signal clock_s: std_ulogic;
signal read_enable_s: std_ulogic;
signal write_enable_s: std_ulogic;
signal write_data_s: std_ulogic_vector(15 downto 0);
signal fifo_gsr_s: std_ulogic;
signal read_data_s: std_ulogic_vector(15 downto 0);
signal full_s: std_ulogic;
signal empty_s: std_ulogic;
signal fifocount_s: std_ulogic_vector(7 downto 0);

begin
u1: fifoctlr_cc
port map(
clock_in => clock_s,
read_enable_in => read_enable_s,
write_enable_in => write_enable_s,
write_data_in => write_data_s,
fifo_gsr_in => fifo_gsr_s,
read_data_out => read_data_s,
full_out => full_s,
empty_out => empty_s,
fifocount_out => fifocount_s
);


-- *** Test Bench - User Defined Section ***
clock: process
begin
[...]
__________________________________________________

please help me!!

Thank you, Simone

-------------------------------------------------------------------
Simone Winkler
Mechatronik-Studentin / Universität Linz
simone.winkler@students.jku.at
ICQ: 20212150
Click to expand...
 
before you start the simulation, you should compile the X's library for the
simulator (use the 'compxlib' command).
There's several documents on X's website mentioned how to do this.

"Simone Winkler" <simone.winkler@gmx.at>
??????:1066686601.590067@news.liwest.at...
 
You should open a webcase with Xilinx if nothing else helps. I just burned
several days trying to figure out why Modelsim wouldn't simulate a
chunk-o-code. It complained about "glbl.v". To make a long and painful
story short, there's a bug in the current release of MXE. This will be
fixed in the ISE 6.2i release.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"



"Simone Winkler" <simone.winkler@gmx.at> wrote in message
news:1066686601.590067@news.liwest.at...
Hello!

I'm performing a VHDL design for a Xilinx Spartan2-FPGA that implements a
synchronous FIFO.
Actually, at the moment, I'm just using the Application Note Design
offered
on the Xilinx Wepage (XAPP175).
So far, so good, I've got a testbench to be run in Modelsim.
But every time it tells me the following things:

___________________________________________________________________

# Reading D:/Programme/Modeltech_xe/tcl/vsim/pref.tcl
# do fifo_c_tb.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fifoctlr_cc
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture fifoctlr_cc_hdl of fifoctlr_cc
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity fifoctlr_cc
# WARNING[1]: fifo_c.vhd(97): No default binding for component: "bufgp".
(No
entity named "bufgp" was found)
# WARNING[1]: fifo_c.vhd(110): No default binding for component:
"ramb4_s8_s8". (No entity named "ramb4_s8_s8" was found)
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fifo_c_tb
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture test of fifo_c_tb
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity fifo_c_tb
# -- Loading entity fifoctlr_cc
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port write_data_in
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port read_data_out
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port fifocount_out
# WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this
component instantiation will result in an elaboration error.
# vsim -L xilinxcorelib -lib work -t 1ps testbench
# ** Warning: A ModelSim starter license was detected and will be used,
even
though you have installed ModelSim XE. You should obtain an XE license in
order to access ModelSim XE's full capabilities.# Loading
D:/Programme/Modeltech_xe/win32xoem/../std.standard
# ** Error: (vsim-3173) Entity 'work.testbench' has no architecture.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./fifo_c_tb.fdo PAUSED at line 9
__________________________________________________________________


The two components RAMB4_S1 and BUFGP should be in a library - so i don't
understand why it's not found.
I don't understand, why the ports don't match - they are really the same
type (most of them std_ulogic(_vector)).
And at the end, why does it say "Entity 'work.testbench' has no
architecture" ?
My idea is that i need a configuration file. But i'm doing everything out
of
Xilinx ISE Webpack, there i never need a configuration file, or do i? I'm
quite out of understanding at the moment...:(.



My TestBench-Code (at least parts of it) was:
___________________________________________

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;

entity fifo_c_tb is
end fifo_c_tb;

architecture test of fifo_c_tb is
component fifoctlr_cc
port (clock_in: in std_ulogic;
read_enable_in: in std_ulogic;
write_enable_in: in std_ulogic;
write_data_in: in std_ulogic_vector(15 downto 0);
fifo_gsr_in: in std_ulogic;
read_data_out: out std_ulogic_vector(15 downto 0);
full_out: out std_ulogic;
empty_out: out std_ulogic;
fifocount_out: out std_ulogic_vector(7 downto 0));
end component;

constant clk_delay_c : time := 50 ns;

signal clock_s: std_ulogic;
signal read_enable_s: std_ulogic;
signal write_enable_s: std_ulogic;
signal write_data_s: std_ulogic_vector(15 downto 0);
signal fifo_gsr_s: std_ulogic;
signal read_data_s: std_ulogic_vector(15 downto 0);
signal full_s: std_ulogic;
signal empty_s: std_ulogic;
signal fifocount_s: std_ulogic_vector(7 downto 0);

begin
u1: fifoctlr_cc
port map(
clock_in => clock_s,
read_enable_in => read_enable_s,
write_enable_in => write_enable_s,
write_data_in => write_data_s,
fifo_gsr_in => fifo_gsr_s,
read_data_out => read_data_s,
full_out => full_s,
empty_out => empty_s,
fifocount_out => fifocount_s
);


-- *** Test Bench - User Defined Section ***
clock: process
begin
[...]
__________________________________________________

please help me!!

Thank you, Simone

-------------------------------------------------------------------
Simone Winkler
Mechatronik-Studentin / Universität Linz
simone.winkler@students.jku.at
ICQ: 20212150
Click to expand...
 
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