Please help me! strange thing: Cadence ICFB extraction vs. s

W

walala

Guest
Dear all,

I am puzzled by the following strange things and would you mind giving me
some advice?

I recently designed a fairly large circuit. The DRC time is about 2-3 hours.
The layout -> extract view time is about 3-4 hours. But strangely enough,
the spectre netlister netlist extraction is already run for 6 days and still
running endlessly... The program shows by "top"

PID USERNAME THR PRI NICE SIZE RES STATE TIME CPU
19652 xding 1 20 0 1255M 918M run 120.5H 49.52% si

And the computer is dual 750MHz SUN.

I am using the spectre option directly in ICFB tools menu, not through
Analog Artist, and it is not spectreS...

I expect the time for layout-> extract and netlist extraction time should be
the same, but why it takes 6 days without ending?

Please help me! Thank you very much,

-Walala
 
"walala" <mizhael@yahoo.com> wrote in message news:<bmg3bp$a2g$1@mozo.cc.purdue.edu>...
I recently designed a fairly large circuit. The DRC time is about 2-3 hours.
The layout -> extract view time is about 3-4 hours. But strangely enough,
the spectre netlister netlist extraction is already run for 6 days and still
running endlessly... The program shows by "top"

PID USERNAME THR PRI NICE SIZE RES STATE TIME CPU
19652 xding 1 20 0 1255M 918M run 120.5H 49.52% si
I assume the DRC/extract run times are for Diva; if so, the circuit
is not *terribly* big. Certainly many before you have run larger.

You would usually expect netlisting time to be fast compared to
Diva DRC/extract, even if the netlist is flat, so you've either
got something broken, or pathologically configured.

Your si process size is bigger than I've ever seen. You're not
out of RAM (you're currently getting 99% of one CPU, on a 918MB
resident set size).

First, 'truss -p' the si process and make sure it's not doing something
dumb (hammering a full file system or something).

Go to the simulation run directory and see what the log file looks
like, and the output file(s).

Try netlisting sub-blocks, moving up one level of hierarchy at
a time until trouble hits.

-Jay-
 
"Jay Lessert" <jayl-news@accelerant.net> wrote in message
news:7109f92b.0310141346.49e386c2@posting.google.com...
"walala" <mizhael@yahoo.com> wrote in message
news:<bmg3bp$a2g$1@mozo.cc.purdue.edu>...
I recently designed a fairly large circuit. The DRC time is about 2-3
hours.
The layout -> extract view time is about 3-4 hours. But strangely
enough,
the spectre netlister netlist extraction is already run for 6 days and
still
running endlessly... The program shows by "top"

PID USERNAME THR PRI NICE SIZE RES STATE TIME CPU
19652 xding 1 20 0 1255M 918M run 120.5H 49.52% si

I assume the DRC/extract run times are for Diva; if so, the circuit
is not *terribly* big. Certainly many before you have run larger.

You would usually expect netlisting time to be fast compared to
Diva DRC/extract, even if the netlist is flat, so you've either
got something broken, or pathologically configured.

Your si process size is bigger than I've ever seen. You're not
out of RAM (you're currently getting 99% of one CPU, on a 918MB
resident set size).

First, 'truss -p' the si process and make sure it's not doing something
dumb (hammering a full file system or something).

Go to the simulation run directory and see what the log file looks
like, and the output file(s).

Try netlisting sub-blocks, moving up one level of hierarchy at
a time until trouble hits.

Dear Jay,

I killed that process, and rerun the netlisting. This time I use IC50.

And it hung again,

this time there is even no ****.pdv files generated... and the disk quota is
always unchanged.

the last line of the log file: si.foregnd.log

------------------------------------------------------------
Begin Incremental Netlisting Oct 14 22:16:14 2003
Loading the file
'/package/cae/cadence/ic50/tools.sun4v/dfII/etc/skill/hnl/spectre.ile'.si:
Loadi
ng file
"/package/cae/cadence/ic50/tools.sun4v/dfII/etc/skill/hnl/spectre.ile".
Loading the file
'/package/cae/cadence/ic50/tools.sun4v/dfII/etc/skill/hnl/driver.ile'.si:
Loadin
g file
"/package/cae/cadence/ic50/tools.sun4v/dfII/etc/skill/hnl/driver.ile".
Begin Incremental Netlisting Oct 14 22:16:14 2003
--------
then it hung...


Could you please help me out this swamp?


Thank you ,

-Walala
 
"walala" <mizhael@yahoo.com> wrote in message news:<bmii1s$li3$1@mozo.cc.purdue.edu>...
"Jay Lessert" <jayl-news@accelerant.net> wrote in message
news:7109f92b.0310141346.49e386c2@posting.google.com...
Go to the simulation run directory and see what the log file looks
like, and the output file(s).

Try netlisting sub-blocks, moving up one level of hierarchy at
a time until trouble hits.
You should try this.

"/package/cae/cadence/ic50/tools.sun4v/dfII/etc/skill/hnl/driver.ile".
Begin Incremental Netlisting Oct 14 22:16:14 2003
--------
That's normal. If no errors, the next and final line is
"End netlisting".

In your previous message, the truss output shows you writing
an output netlist, and growing the process size.

I have a suspicion you are trying to netlist a very large,
flat cell. Is that correct?

-Jay-
 
"Jay Lessert" <jayl-news@accelerant.net> wrote in message
news:7109f92b.0310141346.49e386c2@posting.google.com...
"walala" <mizhael@yahoo.com> wrote in message
news:<bmg3bp$a2g$1@mozo.cc.purdue.edu>...
I recently designed a fairly large circuit. The DRC time is about 2-3
hours.
The layout -> extract view time is about 3-4 hours. But strangely
enough,
the spectre netlister netlist extraction is already run for 6 days and
still
running endlessly... The program shows by "top"

PID USERNAME THR PRI NICE SIZE RES STATE TIME CPU
19652 xding 1 20 0 1255M 918M run 120.5H 49.52% si

I assume the DRC/extract run times are for Diva; if so, the circuit
is not *terribly* big. Certainly many before you have run larger.

You would usually expect netlisting time to be fast compared to
Diva DRC/extract, even if the netlist is flat, so you've either
got something broken, or pathologically configured.

Your si process size is bigger than I've ever seen. You're not
out of RAM (you're currently getting 99% of one CPU, on a 918MB
resident set size).

First, 'truss -p' the si process and make sure it's not doing something
dumb (hammering a full file system or something).

Go to the simulation run directory and see what the log file looks
like, and the output file(s).

Try netlisting sub-blocks, moving up one level of hierarchy at
a time until trouble hits.

-Jay-
Dear Jay,

Thank you for your answer! Yeah I am using Diva...

Here is my truss -p result:

write(11, " o r c = 2 . 3 3 7 1 2".., 8192) = 8192
brk(0x4F61BC00) = 0
brk(0x4F61DC00) = 0
brk(0x4F61DC00) = 0
brk(0x4F61FC00) = 0
brk(0x4F61FC00) = 0
brk(0x4F621C00) = 0
getpid() = 19652 [19651]
open("/proc/19652/usage", O_RDONLY) = 12
read(12, "\0\0\0\0\0\0\001\08AB782".., 256) = 256
close(12) = 0
getpid() = 19652 [19651]
open("/proc/19652/usage", O_RDONLY) = 12
read(12, "\0\0\0\0\0\0\001\08AB785".., 256) = 256
close(12) = 0
write(11, " _ n e t 7 6 0 _ n e t".., 8192) = 8192
write(11, " 1 e - 1 6 m = 1\n _ i".., 8192) = 8192
brk(0x4F621C00) = 0
brk(0x4F623C00) = 0
brk(0x4F623C00) = 0
brk(0x4F625C00) = 0
brk(0x4F625C00) = 0
brk(0x4F627C00) = 0
brk(0x4F627C00) = 0
brk(0x4F629C00) = 0
getpid() = 19652 [19651]
open("/proc/19652/usage", O_RDONLY) = 12
read(12, "\0\0\0\0\0\0\001\08AB7FA".., 256) = 256
close(12) = 0
brk(0x4F629C00) = 0
brk(0x4F639C00) = 0
getpid() = 19652 [19651]
open("/proc/19652/usage", O_RDONLY) = 12
read(12, "\0\0\0\0\0\0\001\08AB7FD".., 256) = 256
close(12) = 0
write(11, " 7 2 6 _ n e t 2 2 7 5".., 8192) = 8192
write(11, " t o r c = 2 . 8 2 6 5".., 8192) = 8192
brk(0x4F639C00) = 0
brk(0x4F63BC00) = 0
brk(0x4F63BC00) = 0
brk(0x4F63DC00) = 0
brk(0x4F63DC00) = 0
brk(0x4F63FC00) = 0
getpid() = 19652 [19651]
open("/proc/19652/usage", O_RDONLY) = 12
read(12, "\0\0\0\0\0\0\001\08AB8 r".., 256) = 256
close(12) = 0
getpid() = 19652 [19651]
open("/proc/19652/usage", O_RDONLY) = 12
read(12, "\0\0\0\0\0\0\001\08AB8 t".., 256) = 256
close(12) = 0

I did not found any problem, then I went to the sprectre.run1 directory,

there is a log file, but it was not updated for 6 days...

and the *******.pdv files are still there, last updated 6 days ago...


After checking all these and reading what you said "netlisting should be
faster than DRC" under the same configuration conditions, I decided to kill
the process and re-do the work...

I guess the only cause for the hang-up would be "I selected to run the
netlisting at background, with priority 0" 6 days ago...

This time I let netlisting to run in foreground with again priority 0, and I
estimate it should at most need 4 hours to finish,...

By the way, I am using IC 446, is there any hidden settings for netlisting?
Memory size, language size, etc? I am directly using it from Tools menu,
choose spectre from Tools menu, then a new menu item will show spectre
simulation, and then I initialize, etc. I did not do netlisting through
Analog Artist Environment... it was said that one is more error prone...


Please give me further comments on what could be going wrong and what should
be improved?

Thanks a lot,

-Walala
 

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