Please help ! It's urgent

C

cocovina

Guest
Hi all

I'm doing with a VHDL program with the concurrent block statement. Here is
my code stuff

entity two_s_complement is
port (INPUT,CLOCK :in bit; OUTPUT : out bit);
end two_s_complement;

architecture behavior of two_s_complement is

begin
outer_block: block (CLOCK = '1' and not CLOCK'stable)
type state is (STATE_A, STATE_B);
signal present_state : state := STATE_A;
begin
A: block ((present_state = STATE_A) and guard)
begin
present_state <=guarded STATE_A when INPUT = '0' else STATE_B;
end block A;

B: block ((present_state = STATE_B) and guard)
begin
present_state <= guarded STATE_B;
end block B;

OUTPUT <= '0' when present_state = STATE_A and INPUT='0'
else '1' when present_state = STATE_A and INPUT='1'
else '0' when present_state = STATE_B and INPUT='1'
else '1';

end block outer_block ;

end behavior;


When I complile it, I encounter the error message "Nonresolved signal
present_state has multiple sources". I've read some post in forum but
cannot find the same case like this. If anyone can help me, I'll really
appreciate. And pls ASAP, it's so urgent !

Thanks
 
cocovina wrote:
I'm doing with a VHDL program with the concurrent block statement. Here is
my code stuff

entity two_s_complement is
port (INPUT,CLOCK :in bit; OUTPUT : out bit);
end two_s_complement;

architecture behavior of two_s_complement is

begin
outer_block: block (CLOCK = '1' and not CLOCK'stable)
type state is (STATE_A, STATE_B);
signal present_state : state := STATE_A;
begin
A: block ((present_state = STATE_A) and guard)
begin
present_state <=guarded STATE_A when INPUT = '0' else STATE_B;
end block A;

B: block ((present_state = STATE_B) and guard)
begin
present_state <= guarded STATE_B;
end block B;

OUTPUT <= '0' when present_state = STATE_A and INPUT='0'
else '1' when present_state = STATE_A and INPUT='1'
else '0' when present_state = STATE_B and INPUT='1'
else '1';

end block outer_block ;

end behavior;


When I complile it, I encounter the error message "Nonresolved signal
present_state has multiple sources". I've read some post in forum but
cannot find the same case like this. If anyone can help me, I'll really
appreciate. And pls ASAP, it's so urgent !
Click to expand...
bit isn't a resolved type, hence the "nonresolved signal has multple
sources" error. Try using std_logic instead.

-a
 
Thanks

I can do it now. Present_state is a resolved signal and it should have
resolved function accompanied.

Anyways. Thanks for your help


bit isn't a resolved type, hence the "nonresolved signal has multple
sources" error. Try using std_logic instead.

-a
Click to expand...


cocovina wrote:
Hi all

I'm doing with a VHDL program with the concurrent block statement. Here is
my code stuff

entity two_s_complement is
port (INPUT,CLOCK :in bit; OUTPUT : out bit);
end two_s_complement;

architecture behavior of two_s_complement is

begin
outer_block: block (CLOCK = '1' and not CLOCK'stable)
type state is (STATE_A, STATE_B);
signal present_state : state := STATE_A;
begin
A: block ((present_state = STATE_A) and guard)
begin
present_state <=guarded STATE_A when INPUT = '0' else STATE_B;
end block A;

B: block ((present_state = STATE_B) and guard)
begin
present_state <= guarded STATE_B;
end block B;

OUTPUT <= '0' when present_state = STATE_A and INPUT='0'
else '1' when present_state = STATE_A and INPUT='1'
else '0' when present_state = STATE_B and INPUT='1'
else '1';

end block outer_block ;

end behavior;


When I complile it, I encounter the error message "Nonresolved signal
present_state has multiple sources". I've read some post in forum but
cannot find the same case like this. If anyone can help me, I'll really
appreciate. And pls ASAP, it's so urgent !

Thanks
Click to expand...
 
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