playing with the NE556 chip again; more questions

A

Adam Funk

Guest
This time I built two astable circuits, using different designs (from
the same book), on the two timers in one TI NE556 chip.

Timer A:

reset pin --- Vcc

discharge pin --- not connected

control pin --- not connected

output --/\/\-- trigger & threshold --|(-- ground

Timer B:

reset pin --- Vcc

Vcc --/\/\-- discharge --/\/\--- trigger & threshold --|(- ground
| |
|--|>|--|
1N4148


To avoid confusion (as generated by my previous post), I've used pin
names rather than numbers. The 556's ground & Vcc pins are connected
normally to a 9 V battery. The output of each timer is a 470 Ί
resistor in series with an LED (so 20 mA on each output, well under
the 200 mA recommended limit in the specs).


Circuit A provides equal mark & space times, with a total of 1.4×R×C.
Circuit B is supposed to have independent mark & space times, each
0.7×R×C.

I've wired them up with R=6.9k ~ (for A and for each resistance in B)
and C=100 ¾F (on each timer), which gives a theoretical mark+space of
0.96 sec for both circuits.

At some point, I noticed that application note PDF for the
Philips version of this chip strongly recommends connecting the
control pin through a 10 nF capacitor to ground if you're not using
the control function (to protect the timer from noise). So I wired
one between each control pin & ground.


I've only seen circuit A in this book; other sources only give circuit
B and say to use the same resistance in both positions if you want
equal mark & space. Is circuit B better than A? Why?


The two circuits seem to interfere with each other, and the control
bypass capacitors affect the time as well. Lacking fancy equipment, I
measured the mark+space time by timing 10 pulses with a stopwatch &
dividing, and got these results:

with the control bypass capacitors:

timer A with B off: 1.1 sec
timer B with A off: 0.9 sec
timer A with B on: 0.6 sec
timer B with A on: 0.6 sec

without the capacitors:

timer A with B off: 1.2 sec
timer B with A off: 1.0 sec
timer A with B on: 1.3 sec
timer B with A on: 0.9 sec

Should they interfere this way, or have I goofed something up?


--
Nam Sibbyllam quidem Cumis ego ipse oculis meis vidi in ampulla
pendere, et cum illi pueri dicerent: beable beable beable; respondebat
illa: doidy doidy doidy. [plorkwort]
 
Adam Funk wrote:

This time I built two astable circuits, using different designs (from
the same book), on the two timers in one TI NE556 chip.

Timer A:

reset pin --- Vcc

discharge pin --- not connected

control pin --- not connected

output --/\/\-- trigger & threshold --|(-- ground

Timer B:

reset pin --- Vcc

Vcc --/\/\-- discharge --/\/\--- trigger & threshold --|(- ground
| |
|--|>|--|
1N4148


To avoid confusion (as generated by my previous post), I've used pin
names rather than numbers. The 556's ground & Vcc pins are connected
normally to a 9 V battery. The output of each timer is a 470 Ί
resistor in series with an LED (so 20 mA on each output, well under
the 200 mA recommended limit in the specs).


Circuit A provides equal mark & space times, with a total of 1.4×R×C.
Circuit B is supposed to have independent mark & space times, each
0.7×R×C.

I've wired them up with R=6.9k ~ (for A and for each resistance in B)
and C=100 ÂľF (on each timer), which gives a theoretical mark+space of
0.96 sec for both circuits.

At some point, I noticed that application note PDF for the
Philips version of this chip strongly recommends connecting the
control pin through a 10 nF capacitor to ground if you're not using
the control function (to protect the timer from noise). So I wired
one between each control pin & ground.


I've only seen circuit A in this book; other sources only give circuit
B and say to use the same resistance in both positions if you want
equal mark & space. Is circuit B better than A? Why?


The two circuits seem to interfere with each other, and the control
bypass capacitors affect the time as well. Lacking fancy equipment, I
measured the mark+space time by timing 10 pulses with a stopwatch &
dividing, and got these results:

with the control bypass capacitors:

timer A with B off: 1.1 sec
timer B with A off: 0.9 sec
timer A with B on: 0.6 sec
timer B with A on: 0.6 sec

without the capacitors:

timer A with B off: 1.2 sec
timer B with A off: 1.0 sec
timer A with B on: 1.3 sec
timer B with A on: 0.9 sec

Should they interfere this way, or have I goofed something up?


The control input is sensitive and any little wiggle in the common
circuit for that cap is going to propagate and cause some shift in the
timer.

Try attaching the low side of the bypass caps to a common trace/path
directly to the (-) rail with nothing else connected to that rail between..

Your readings with the use of the bypass cap on the control pin are
most likely more accurate to what you should be getting with the set up
you have also, you must remember the 556 uses a single power rail inside
for both units, one unit could offset the other depending on what they
are doing. In cases like these, you use 2 555's instead.

Jamie
 
On Tue, 28 Feb 2012 17:47:17 +0000, Adam Funk <a24061@ducksburg.com>
wrote:

This time I built two astable circuits, using different designs (from
the same book), on the two timers in one TI NE556 chip.

Timer A:

reset pin --- Vcc

discharge pin --- not connected

control pin --- not connected

output --/\/\-- trigger & threshold --|(-- ground

Timer B:

reset pin --- Vcc

Vcc --/\/\-- discharge --/\/\--- trigger & threshold --|(- ground
| |
|--|>|--|
1N4148


To avoid confusion (as generated by my previous post), I've used pin
names rather than numbers. The 556's ground & Vcc pins are connected
normally to a 9 V battery. The output of each timer is a 470 ?
resistor in series with an LED (so 20 mA on each output, well under
the 200 mA recommended limit in the specs).


Circuit A provides equal mark & space times, with a total of 1.4×R×C.
Circuit B is supposed to have independent mark & space times, each
0.7×R×C.

I've wired them up with R=6.9k ~ (for A and for each resistance in B)
and C=100 ľF (on each timer), which gives a theoretical mark+space of
0.96 sec for both circuits.

At some point, I noticed that application note PDF for the
Philips version of this chip strongly recommends connecting the
control pin through a 10 nF capacitor to ground if you're not using
the control function (to protect the timer from noise). So I wired
one between each control pin & ground.


I've only seen circuit A in this book; other sources only give circuit
B and say to use the same resistance in both positions if you want
equal mark & space. Is circuit B better than A?
---
Yes.
---

---
A bipolar 556's output impedance varies depending on whether it's
sourcing or sinking current, so the charge and discharge currents into
the timing cap will make the mark and space times different.
---


The two circuits seem to interfere with each other, and the control
bypass capacitors affect the time as well. Lacking fancy equipment, I
measured the mark+space time by timing 10 pulses with a stopwatch &
dividing, and got these results:

with the control bypass capacitors:

timer A with B off: 1.1 sec
timer B with A off: 0.9 sec
timer A with B on: 0.6 sec
timer B with A on: 0.6 sec

without the capacitors:

timer A with B off: 1.2 sec
timer B with A off: 1.0 sec
timer A with B on: 1.3 sec
timer B with A on: 0.9 sec

Should they interfere this way, or have I goofed something up?
---
The capacitor on the control input is unnecessary, and you've
neglected to add the mandatory bypass cap from Vcc to GND.

It should be wired directly across Vcc and GND, and for the best
mark-space symmetry you should add another diode to charge-discharge
circuitry.

You could also lower the drain on the supply by changing the charging
cap to 1ľF and raising R1 and R2 to 680k, like this:


..+15>--+-------------------------------------+
.. | |
.. [680k]R1 +---------+ |
.. | |_ | |
.. +--------------------O|D OUT|-----|--[470]--+
.. | R2 D1 | _| | |
.. +-[680k]-[<1N4148]-+--|TH R|O----+ |
.. | | |__ | | |A
.. +-[1N4148>]-+------+-O|TR Vcc|-----+ [LED]
.. D2 | | GND | | |
.. [1ľF] +----+----+ [0.1ľF] |
.. |C1 | |C2 |
..GND>--------------+--------------+----------+---------+

Also, here's a simulation you can run:

Version 4
SHEET 1 880 748
WIRE 352 192 -128 192
WIRE 672 192 576 192
WIRE -128 256 -128 192
WIRE -80 256 -128 256
WIRE 32 256 0 256
WIRE 352 256 32 256
WIRE 640 256 576 256
WIRE 32 320 32 256
WIRE 64 320 32 320
WIRE 176 320 144 320
WIRE 304 320 240 320
WIRE 352 320 304 320
WIRE 736 320 576 320
WIRE 608 384 576 384
WIRE 32 416 32 320
WIRE 64 416 32 416
WIRE 304 416 304 320
WIRE 304 416 128 416
WIRE 736 416 736 320
WIRE 304 480 304 416
WIRE 640 480 640 256
WIRE 640 480 304 480
WIRE -128 512 -128 256
WIRE 608 512 608 384
WIRE 608 512 -128 512
WIRE -128 528 -128 512
WIRE 304 544 304 480
WIRE -128 624 -128 608
WIRE 304 624 304 608
WIRE 304 624 -128 624
WIRE 672 624 672 192
WIRE 672 624 304 624
WIRE 736 624 736 496
WIRE 736 624 672 624
WIRE -128 688 -128 624
FLAG -128 688 0
SYMBOL Misc\\NE555 464 288 M0
SYMATTR InstName U1
SYMBOL voltage -128 512 M0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL res -96 240 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 58 VTop 2
SYMATTR InstName R1
SYMATTR Value 680k
SYMBOL res 48 304 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 680k
SYMBOL res 752 400 M0
WINDOW 0 -45 40 Left 2
WINDOW 3 -59 71 Left 2
SYMATTR InstName R3
SYMATTR Value 1000
SYMBOL cap 320 544 M0
WINDOW 0 -33 32 Left 2
WINDOW 3 -39 58 Left 2
SYMATTR InstName C1
SYMATTR Value 1ľ
SYMBOL diode 64 432 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL diode 240 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N4148
TEXT 88 656 Right 2 !.tran 5 startup uic
TEXT 584 176 Left 2 ;1
TEXT 584 240 Left 2 ;2
TEXT 584 304 Left 2 ;3
TEXT 584 360 Left 2 ;4
TEXT 328 368 Left 2 ;5
TEXT 328 304 Left 2 ;6
TEXT 328 240 Left 2 ;7
TEXT 328 176 Left 2 ;8

You'll need LTspice to run it, and it's available, free, at:

http://www.linear.com/designtools/software/

Once you have it installed, copy the circuit list above and paste it
to a file named anything you like, but with a .asc extension. Then
left-click on the file and LTspice will find it and open it,
displaying the schematic.

Next, you can either right-click the gray area of the schematic and
then left-click "RUN", or left-click the running man icon on the
toolbar to run the simulation.

Use the mouse to run the cursor over to any point you want to probe,
and when you get close enough the cursor will change into a pointy
probe. Then, left click and the wavform at that point will appear on
the plot pane.

Have fun! :)

--
JF
 
On 2012-02-28, Adam Funk <a24061@ducksburg.com> wrote:
This time I built two astable circuits, using different designs (from
the same book), on the two timers in one TI NE556 chip.

A

output --/\/\-- trigger & threshold --|(-- ground

B

Vcc --/\/\-- discharge --/\/\--- trigger & threshold --|(- ground
| |
|--|>|--|
1N4148

Circuit A provides equal mark & space times, with a total of 1.4×R×C.
Circuit B is supposed to have independent mark & space times, each
0.7×R×C.

I've wired them up with R=6.9k ~ (for A and for each resistance in B)
and C=100 ¾F (on each timer), which gives a theoretical mark+space of
0.96 sec for both circuits.

I've only seen circuit A in this book; other sources only give circuit
B and say to use the same resistance in both positions if you want
equal mark & space. Is circuit B better than A? Why?
"A" works best win CMOS devices where the output goes all the way up to
the positive supply voltage and all the way down to ground.

"B" is better in Bipolar (like the NE555 and NE556) where the output
is not symmetrical and the two resistors can be varied to balance the
ratio.

The two circuits seem to interfere with each other, and the control
bypass capacitors affect the time as well. Lacking fancy equipment, I
measured the mark+space time by timing 10 pulses with a stopwatch &
dividing, and got these results:

with the control bypass capacitors:

timer A with B off: 1.1 sec
timer B with A off: 0.9 sec
timer A with B on: 0.6 sec
timer B with A on: 0.6 sec

without the capacitors:

timer A with B off: 1.2 sec
timer B with A off: 1.0 sec
timer A with B on: 1.3 sec
timer B with A on: 0.9 sec

Should they interfere this way, or have I goofed something up?
They should be fully independant. check that the powersupply pins
and timing capacitors are wired correctly.

--
⚂⚃ 100% natural
 
On 1 Mar 2012 08:48:32 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

On 2012-02-28, Adam Funk <a24061@ducksburg.com> wrote:
This time I built two astable circuits, using different designs (from
the same book), on the two timers in one TI NE556 chip.


A

output --/\/\-- trigger & threshold --|(-- ground


B

Vcc --/\/\-- discharge --/\/\--- trigger & threshold --|(- ground
| |
|--|>|--|
1N4148

Circuit A provides equal mark & space times, with a total of 1.4×R×C.
Circuit B is supposed to have independent mark & space times, each
0.7×R×C.

I've wired them up with R=6.9k ~ (for A and for each resistance in B)
and C=100 ľF (on each timer), which gives a theoretical mark+space of
0.96 sec for both circuits.

I've only seen circuit A in this book; other sources only give circuit
B and say to use the same resistance in both positions if you want
equal mark & space. Is circuit B better than A? Why?

"A" works best win CMOS devices where the output goes all the way up to
the positive supply voltage and all the way down to ground.

"B" is better in Bipolar (like the NE555 and NE556) where the output
is not symmetrical and the two resistors can be varied to balance the
ratio.
---
The output has nothing to do with the charge and discharge times in
"B".

--
JF
 
On 2012-02-28, Jamie wrote:

The control input is sensitive and any little wiggle in the common
circuit for that cap is going to propagate and cause some shift in the
timer.

Try attaching the low side of the bypass caps to a common trace/path
directly to the (-) rail with nothing else connected to that rail between..
That does make them a bit more consistent --- I wouldn't have expected
breadboard leads to have much effect at low frequencies like this.


Your readings with the use of the bypass cap on the control pin are
most likely more accurate to what you should be getting with the set up
you have also, you must remember the 556 uses a single power rail inside
for both units, one unit could offset the other depending on what they
are doing. In cases like these, you use 2 555's instead.
OK. I expected that by keeping the output current below 20 mA on each
side, the single power rail effect would be insignificant.


As it turns out, though, I get the biggest improvement in consistency
by using the reset pins properly to switch the timers on & off (reset
to Vcc for on, to ground for off), instead of just pulling one of the
wires so the LED stops blinking. Doing it that way (with the control
bypass capacitors grounded more tightly gives these:

A with B on: 1.2 sec
B with A on: 1.2 sec
A with B off: 1.2 sec
B with A off: 1.0 sec

which could be within stopwatch measuring error.


Thanks!


--
XML is like violence: if it doesn't solve the problem,
use more.
 
On Thu, 8 Mar 2012, Adam Funk wrote:

On 2012-02-28, Jamie wrote:

The control input is sensitive and any little wiggle in the common
circuit for that cap is going to propagate and cause some shift in the
timer.

Try attaching the low side of the bypass caps to a common trace/path
directly to the (-) rail with nothing else connected to that rail between..

That does make them a bit more consistent --- I wouldn't have expected
breadboard leads to have much effect at low frequencies like this.

It shouldn't at those frequencies.

I've never bypassed the control pin when I've used 555s.

Michael

Your readings with the use of the bypass cap on the control pin are
most likely more accurate to what you should be getting with the set up
you have also, you must remember the 556 uses a single power rail inside
for both units, one unit could offset the other depending on what they
are doing. In cases like these, you use 2 555's instead.

OK. I expected that by keeping the output current below 20 mA on each
side, the single power rail effect would be insignificant.


As it turns out, though, I get the biggest improvement in consistency
by using the reset pins properly to switch the timers on & off (reset
to Vcc for on, to ground for off), instead of just pulling one of the
wires so the LED stops blinking. Doing it that way (with the control
bypass capacitors grounded more tightly gives these:

A with B on: 1.2 sec
B with A on: 1.2 sec
A with B off: 1.2 sec
B with A off: 1.0 sec

which could be within stopwatch measuring error.


Thanks!


--
XML is like violence: if it doesn't solve the problem,
use more.
 
On 2012-02-29, John Fields wrote:

On Tue, 28 Feb 2012 17:47:17 +0000, Adam Funk <a24061@ducksburg.com
wrote:

I've only seen circuit A in this book; other sources only give circuit
B and say to use the same resistance in both positions if you want
equal mark & space. Is circuit B better than A?

---
Yes.
---

Why?

---
A bipolar 556's output impedance varies depending on whether it's
sourcing or sinking current, so the charge and discharge currents into
the timing cap will make the mark and space times different.
That makes sense, thanks.


The capacitor on the control input is unnecessary,
Aha, the TI data sheet shows the 0.01 ÂľF from CONT to GND in the
monostable example, but for the astable example circuit, it shows CONT
open but with the note "Bypassing the control-voltage input to ground
with a capacitor might improve operation. This should be evaluated for
individual applications." Fairly ambivalent.


and you've neglected to add the mandatory bypass cap from Vcc to
GND. It should be wired directly across Vcc and GND, and for the
best mark-space symmetry you should add another diode to
charge-discharge circuitry.

OK, I'll try those & see how they improve things.


You could also lower the drain on the supply by changing the charging
cap to 1ÂľF and raising R1 and R2 to 680k, like this:


.+15>--+-------------------------------------+
. | |
. [680k]R1 +---------+ |
. | |_ | |
. +--------------------O|D OUT|-----|--[470]--+
. | R2 D1 | _| | |
. +-[680k]-[<1N4148]-+--|TH R|O----+ |
. | | |__ | | |A
. +-[1N4148>]-+------+-O|TR Vcc|-----+ [LED]
. D2 | | GND | | |
. [1ÂľF] +----+----+ [0.1ÂľF] |
. |C1 | |C2 |
.GND>--------------+--------------+----------+---------+
Thanks! ISTR reading that the Rs in the R C timings can range from
1 kΊ to 1 MΊ and work, but I guess (other things being acceptable)
higher resistances are better because they reduce those currents.


Also, here's a simulation you can run:
....
You'll need LTspice to run it, and it's available, free, at:

http://www.linear.com/designtools/software/

Once you have it installed, copy the circuit list above and paste it
to a file named anything you like, but with a .asc extension. Then
left-click on the file and LTspice will find it and open it,
displaying the schematic.
As it turns out, I've got a couple of spice & geda packages available
already on Ubuntu, which I'm working out how to use. Thanks for the
example.


Have fun! :)
Sure, that's the most important part after "don't set anything on
fire".

:)


--
....the reason why so many professional artists drink a lot is not
necessarily very much to do with the artistic temperament, etc. It is
simply that they can afford to, because they can normally take a large
part of a day off to deal with the ravages. [Amis _On Drink_]
 
On Tue, 13 Mar 2012 13:35:36 +0000, Adam Funk <a24061@ducksburg.com>
wrote:

On 2012-02-29, John Fields wrote:

You could also lower the drain on the supply by changing the charging
cap to 1ľF and raising R1 and R2 to 680k, like this:


.+15>--+-------------------------------------+
. | |
. [680k]R1 +---------+ |
. | |_ | |
. +--------------------O|D OUT|-----|--[470]--+
. | R2 D1 | _| | |
. +-[680k]-[<1N4148]-+--|TH R|O----+ |
. | | |__ | | |A
. +-[1N4148>]-+------+-O|TR Vcc|-----+ [LED]
. D2 | | GND | | |
. [1ľF] +----+----+ [0.1ľF] |
. |C1 | |C2 |
.GND>--------------+--------------+----------+---------+

Thanks! ISTR reading that the Rs in the R C timings can range from
1 k? to 1 M? and work, but I guess (other things being acceptable)
higher resistances are better because they reduce those currents.
---
The reason for lowering the capacitance of C1 is the same reason that
if you had to fill and empty a glass once a second, the smaller the
glass you used, the less water you'd use, which equates to less energy
used in the transaction.

The lowest R1 can be is dictated by how much current the discharge
transistor can take, while the highest R is limited by the leakage
current of C1, TH, and TR\.

--
JF
 
On 2012-03-14, John Fields wrote:

On Tue, 13 Mar 2012 13:35:36 +0000, Adam Funk <a24061@ducksburg.com
wrote:

On 2012-02-29, John Fields wrote:

You could also lower the drain on the supply by changing the charging
cap to 1ÂľF and raising R1 and R2 to 680k, like this:


.+15>--+-------------------------------------+
. | |
. [680k]R1 +---------+ |
. | |_ | |
. +--------------------O|D OUT|-----|--[470]--+
. | R2 D1 | _| | |
. +-[680k]-[<1N4148]-+--|TH R|O----+ |
. | | |__ | | |A
. +-[1N4148>]-+------+-O|TR Vcc|-----+ [LED]
. D2 | | GND | | |
. [1ÂľF] +----+----+ [0.1ÂľF] |
. |C1 | |C2 |
.GND>--------------+--------------+----------+---------+

Thanks! ISTR reading that the Rs in the R C timings can range from
1 k? to 1 M? and work, but I guess (other things being acceptable)
higher resistances are better because they reduce those currents.

---
The reason for lowering the capacitance of C1 is the same reason that
if you had to fill and empty a glass once a second, the smaller the
glass you used, the less water you'd use, which equates to less energy
used in the transaction.

The lowest R1 can be is dictated by how much current the discharge
transistor can take, while the highest R is limited by the leakage
current of C1, TH, and TR\.
Thanks again!


--
Physics is like sex. Sure, it may give some practical results,
but that's not why we do it. [Richard Feynman]
 

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