PlanAhead

R

Roger

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The latest Xilinx PlanAhead seems to do everything that a project needs from
VHDL input to bit stream. So what's ISE for now?

Thanks,
Rog.
 
On Nov 23, 5:00 pm, "Roger" <rogerwil...@hotmail.com> wrote:
The latest Xilinx PlanAhead seems to do everything that a project needs from
VHDL input to bit stream. So what's ISE for now?

Thanks,
Rog.
Click to expand...
My understanding is that the plan is for PlanAhead to replace ISE.
Though I'm not sure at what point this will happen.

Chris
 
"Chris Maryan" wrote in message
news:6092db29-96e8-45ce-8870-9069272dc561@o4g2000yqd.googlegroups.com...

On Nov 23, 5:00 pm, "Roger" <rogerwil...@hotmail.com> wrote:
The latest Xilinx PlanAhead seems to do everything that a project needs
from
VHDL input to bit stream. So what's ISE for now?

Thanks,
Rog.
Click to expand...
My understanding is that the plan is for PlanAhead to replace ISE.
Though I'm not sure at what point this will happen.

Chris

Chris,

Thanks for the reply. I suspected this might be the case. Did you hear this
from Xilinx?

Rog.
 
On Wed, 24 Nov 2010, Roger wrote:

"Chris Maryan" wrote in message
news:6092db29-96e8-45ce-8870-9069272dc561@o4g2000yqd.googlegroups.com...

On Nov 23, 5:00 pm, "Roger" <rogerwil...@hotmail.com> wrote:
The latest Xilinx PlanAhead seems to do everything that a project needs
from
VHDL input to bit stream. So what's ISE for now?

Thanks,
Rog.

My understanding is that the plan is for PlanAhead to replace ISE.
Though I'm not sure at what point this will happen.

Chris

Chris,

Thanks for the reply. I suspected this might be the case. Did you hear this
from Xilinx?

Rog.

I do not have the experience with the newest PlanAhead but we tried the
Click to expand...
dynamic reconfiguration on the ISE11 with PlanAhead and it was not
possible to turn RTL project into partial reconfiguration flow. So i
suspect, that the ISE and planAhead will be moving in different direction.
But it is just my understanding, maybe it was just a bug.

Jan
 
On Nov 24, 3:11 pm, "Roger" <rogerwil...@hotmail.com> wrote:
"Chris Maryan"  wrote in message

news:6092db29-96e8-45ce-8870-9069272dc561@o4g2000yqd.googlegroups.com...

On Nov 23, 5:00 pm, "Roger" <rogerwil...@hotmail.com> wrote:

The latest Xilinx PlanAhead seems to do everything that a project needs
from
VHDL input to bit stream. So what's ISE for now?

Thanks,
Rog.

My understanding is that the plan is for PlanAhead to replace ISE.
Though I'm not sure at what point this will happen.

Chris

Chris,

Thanks for the reply. I suspected this might be the case. Did you hear this
from Xilinx?

Rog.
Click to expand...
I'm not sure where I heard this, it was a while ago. Possibly my AE,
possibly just internet rumors. If you watch some of the demo videos on
the Xilinx website, they tend to be working with planahead
exclusively.

However, the best thing I've ever done for myself is to stop using any
GUI based compile flow. Both Planahead and ISE just run the command
line tools with a specific set of options. Usually those options are
easy to figure (they're in the report files for the tools) out and
stick in a .bat file or a makefile. Though I do like to use PlanAhead
for figuring out area groups and pin planning.

Chris
 
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