Place & route question in Xilinx...

[Kelvin]

After compiling few FPGAs, I have found this phenomenon.
When the design occupies a small fraction of the FPGA, par throws the stuff
loosely spread
all over the FPGA...like ugly zigzags...
When the design occupies 80% of the FPGA, par kompresses my design densely
into the bottom
60% of the FPGA, leaving top 40% loosely occupied...then it tell me it
failed route...
Weird!

What may I do besides manual floorplanning?

Kelvin

 

[jakab tanko]

You can try using the PACE to define area constraints for your design
block(s), that way
PAR will have a predefined location to work with,
---
jakab
"Kelvin" <student@nowhere.com> wrote in message
news:40ea7188@news.starhub.net.sg...

After compiling few FPGAs, I have found this phenomenon.
When the design occupies a small fraction of the FPGA, par throws the
stuff
loosely spread
all over the FPGA...like ugly zigzags...
When the design occupies 80% of the FPGA, par kompresses my design densely
into the bottom
60% of the FPGA, leaving top 40% loosely occupied...then it tell me it
failed route...
Weird!

What may I do besides manual floorplanning?

Kelvin

 

[Kelvin @ SG]

Yeah, when I did partial reconfigurable design, I apply area_group on
two sides of my FPGA. However, the phenomenon remain for each of
the partial designs.

Thanks for your reply.

Kelvin




"jakab tanko" <jtanko@ics-ltd.com> wrote in message
news:cce64d$cbf$1@news.storm.ca...

You can try using the PACE to define area constraints for your design
block(s), that way
PAR will have a predefined location to work with,
---
jakab
"Kelvin" <student@nowhere.com> wrote in message
news:40ea7188@news.starhub.net.sg...
After compiling few FPGAs, I have found this phenomenon.
When the design occupies a small fraction of the FPGA, par throws the
stuff
loosely spread
all over the FPGA...like ugly zigzags...
When the design occupies 80% of the FPGA, par kompresses my design
densely
into the bottom
60% of the FPGA, leaving top 40% loosely occupied...then it tell me it
failed route...
Weird!

What may I do besides manual floorplanning?

Kelvin

 

[John_H]

For a few critical paths it's possible to guide the P&R tool without
resorting to full manual floorplanning. The RLOC (relative location)
constraints allow you to build up a macro of a few critical registers, LUTs,
or other primitives. By specifying where elements in the critical path need
to be relative to each other, the P&R tool has an easier time producing the
results you need. If the number of critical routes is large, this technique
might not be so desireable.

"Kelvin" <student@nowhere.com> wrote in message
news:40ea7188@news.starhub.net.sg...

After compiling few FPGAs, I have found this phenomenon.
When the design occupies a small fraction of the FPGA, par throws the
stuff
loosely spread
all over the FPGA...like ugly zigzags...
When the design occupies 80% of the FPGA, par kompresses my design densely
into the bottom
60% of the FPGA, leaving top 40% loosely occupied...then it tell me it
failed route...
Weird!

What may I do besides manual floorplanning?

Kelvin