Guest
Greetings,
I am trying to save a optimized design (which is multi level i.e., >2)
in PLA format (same as Espresso). I keep getting the message, "Design
is not currently represented as PLA. (PLA0-0)".
Can Synopsys do a multi-level to 2-level conversion? If not what is the
point of supporting PLA format? Of course I could use the original
Espresso for a 2-level optimization and avoid DC alltogether.
I basically want to use this feature of DC for a conversion from
multi-level logic represented by a
Verilog file to a 2-level logic in Espresso format. Can DC do it?
Regards,
Hrh.
I am trying to save a optimized design (which is multi level i.e., >2)
in PLA format (same as Espresso). I keep getting the message, "Design
is not currently represented as PLA. (PLA0-0)".
Can Synopsys do a multi-level to 2-level conversion? If not what is the
point of supporting PLA format? Of course I could use the original
Espresso for a 2-level optimization and avoid DC alltogether.
I basically want to use this feature of DC for a conversion from
multi-level logic represented by a
Verilog file to a 2-level logic in Espresso format. Can DC do it?
Regards,
Hrh.