PKS/BuildGates .LEF file

[Neil]

hi there
i m using pks/buildgates synthesis for my design.i need to set timing
constraints so i m trying to read logical and physical libraries and
set technology library.i m using lca300k.alf but i m having trouble to
find where .lef files r located..
can anybody help me about how to set timing constraints.
thanks
Neil

 

[Muzaffer Kal]

On 13 Jan 2004 11:39:17 -0800, nasicvlsi@yahoo.com (Neil) wrote:

hi there
i m using pks/buildgates synthesis for my design.i need to set timing
constraints so i m trying to read logical and physical libraries and
set technology library.i m using lca300k.alf but i m having trouble to
find where .lef files r located..
can anybody help me about how to set timing constraints.
thanks
Neil

lca300k is an old gate-array technology and probably lsi did the
back-end themselves and never released lef for it. But to set timing
constraints you don't need the lef necessarily. You can get an
estimate for timing just by using the alf.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

 

[Neil]

Hi Muzaffer
can you plz tell me which is the latest technology better than
lca3k.and can you also tell me how to get estimate on timing
constraint(with and withought lca300k)
may be you can write down some guidelines.here is my design flow for
your better idea.
i m using PKS/Buildgates for my design synthesis and layout/placement.

1. i need to load my timing and physical libraries
using "read_lef" command.(according to online manual,if necessary)
2.then i have to set target technology
3.check libraries if physical and timing lib are the
same.
4.then read vhdl files,
5.do_build_generic
6.after this i have to set timing constraints (can u
give some guidelines on this plz)
7.do_optimize
8.then i have to go for place and route
(i didnt reach uptil this point yet,but you can write
something on this,too)

is this design flow accurate.plz suggest.

thanks a lott.
Neil







Muzaffer Kal <kal@dspia.com> wrote in message news:<8uk900du2nhrju1e8nn65n8pcclurcgenu@4ax.com>...

On 13 Jan 2004 11:39:17 -0800, nasicvlsi@yahoo.com (Neil) wrote:

hi there
i m using pks/buildgates synthesis for my design.i need to set timing
constraints so i m trying to read logical and physical libraries and
set technology library.i m using lca300k.alf but i m having trouble to
find where .lef files r located..
can anybody help me about how to set timing constraints.
thanks
Neil

lca300k is an old gate-array technology and probably lsi did the
back-end themselves and never released lef for it. But to set timing
constraints you don't need the lef necessarily. You can get an
estimate for timing just by using the alf.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations