Pipelining question

[Divyang M]

Hi,
I am looking for some insight into how I can go about pipelining my
system.

The system is an image interpolator which contains a buffer (on-chip
dual-port RAM) and an interpolator block.
The buffer stores incoming data (real-time say at X MHz). The
interpolator requires 4 data elements from this buffer to produce 1
output.

To keep the systems real-time, I am running my system at X MHz and also
write to the buffer at this rate. But read the data out of the buffer
at 4X MHz so that at each clock cycle I have all the 4 data elements
that the intepolator unit needs. This has limited X to 50 MHz because
the internal block RAM max out at 200 MHz (well, according to Altera it
can go upto 287 MHz but I hit the wall at some point or another).

I was wondering if there is a way to pipeline the design so that I can
run the whole system at a single clock frequency but still not have a
huge backlog of data accumulation (since there is finite amount of
on-chip storage) or if there are examples of such in any books?

Thanks,
Divyang M

 

[Divyang M]

Hello Kai,

I do not have that much storage space to store the data 4 times since
my data is a 240x320 gray level (8-bit/pixel) image.

The other option I was thinking of is to delay the first of the four
output by 4 cycles (registers), the second by 3 cycles, the third
output by 2 cycles, and the fourth output by 1 cycle. These four
points will then be aligned, but if I use this strategy, then I get a
valid output out of my system once every 4 cycles, so a throughput of
0.25 (if I'm using the definition of throughput correctly). But I would
ideally like the throughput to be 1.

Any others suggestions you have would be welcome.

Thanks,
Divyang M

 

[Divyang M]

Hi Bert,

The four elements are not consecutive. I am actually working with an
image. So the four elements are essentially 2 elements each in 2 rows,
something like A11, A12, A21, A22.

But these can be any 4 "adjacent" elements in the image, so they do not
go by a particular order either.

Thanks,
Divyang

 

[Divyang M]

Hi Bert,

That would work if I was doing a "forward mapping" (ie taking 4 know
input pixels to comupte an output pixel which can end up anywhere in
the image), but I am doing "inverse mapping" (ie I know the output
pixel I am computing, but the 4 input pixels can be located anywhere in
the input image).

Thanks for your time and help.

Divyang

 

[Divyang M]

Hi Ben,

That's what I am thinking now. There seems to be no straight-forward
solution to "inverse mapping" problems (due to the uncertainity of
which input pixels to access) even in any of the literatures. So I
might have to go this way.

Thanks,
Divyang M

 

[Divyang M]

Hi Ben,

Thanks for the insight. I will look carefully at your suggestion and
hopefully it will yield something for my problem as well .

Thanks,
Divyang