Pipelining of FPGA code

[dash82]

Hi,

I am trying to understand what Pipelined designing/architecture for
FPGA's mean ?

I went through documents which list all the benefits of using
pipelining for FPGA's. But, none of them explicitly explained how
pipelined architecture was better (efficiency-wise) against a non-
pipelined architecture. I would'nt generally ask such kind of
questions in a forum. But going through books and
searching in Google didnt help me.

It would help me if someone could point to some article / book /
example (and
preferably a Verilog /VHDL based one) which explains pipelining at in
depth.

Thanks.

Shah.

 

[Thomas Stanka]

On 30 Nov., 06:06, dash82 <dhavalru...@gmail.com> wrote:

I am trying to understand what Pipelined designing/architecture for
FPGA's mean ?

The same as pipelined in any other HW architecture.
A very basic answer is:
The calculation of f = A + ((B + C) * D) could be done in one clock
cycle, which slows down the maximum clock cycle of your device, as the
longest datapath is through two adders and one multiplier.
If you pipeline, you add registers in between and use three clock
cycles to get the result with much faster clock cycles.
f1 = B+C, f2 = f1 * D, f = A + f2
The overall speed for one calculation would slow down a bit, as you
add two register delays and need your clock to be slow enough for the
slowest part of the operation. If you need this operation done for a
datastream, you gain each clock cycle after the second one a new value
for f(t) as f1(t+2) and f2(t+1) is calculated in parallel to f(t).

bye Thomas

 

[David R Brooks]

Thomas Stanka wrote:

On 30 Nov., 06:06, dash82 <dhavalru...@gmail.com> wrote:
I am trying to understand what Pipelined designing/architecture for
FPGA's mean ?

The same as pipelined in any other HW architecture.
A very basic answer is:
The calculation of f = A + ((B + C) * D) could be done in one clock
cycle, which slows down the maximum clock cycle of your device, as the
longest datapath is through two adders and one multiplier.
If you pipeline, you add registers in between and use three clock
cycles to get the result with much faster clock cycles.
f1 = B+C, f2 = f1 * D, f = A + f2
The overall speed for one calculation would slow down a bit, as you
add two register delays and need your clock to be slow enough for the
slowest part of the operation. If you need this operation done for a
datastream, you gain each clock cycle after the second one a new value
for f(t) as f1(t+2) and f2(t+1) is calculated in parallel to f(t).

http://en.wikipedia.org/wiki/Pipelining

 

[dash82]

On Nov 30, 5:51 pm, David R Brooks <daveb...@iinet.net.au> wrote:

Thomas Stanka wrote:
On 30 Nov., 06:06, dash82 <dhavalru...@gmail.com> wrote:
I am trying to understand what Pipelined designing/architecture for
FPGA's mean ?

The same as pipelined in any other HW architecture.
A very basic answer is:
The calculation of f = A + ((B + C) * D) could be done in one clock
cycle, which slows down the maximum clock cycle of your device, as the
longest datapath is through two adders and one multiplier.
If you pipeline, you add registers in between and use three clock
cycles to get the result with much faster clock cycles.
f1 = B+C, f2 = f1 * D, f = A + f2
The overall speed for one calculation would slow down a bit, as you
add two register delays and need your clock to be slow enough for the
slowest part of the operation. If you need this operation done for a
datastream, you gain each clock cycle after the second one a new value
for f(t) as f1(t+2) and f2(t+1) is calculated in parallel to f(t).

http://en.wikipedia.org/wiki/Pipelining

Thank you !