Pipelining Fixed_pkg operations (VHDL 200x-FT)

[Divyang M]

I was wondering if it is possible (and how) to pipeline operations
(such as mult, add, etc) that I use from the Fixed_pkg library?

I am hoping that this will speed up my system a little.
Thanks,
Divyang M

 

[Divyang M]

Hello David,

First of all -- Thank You -- for putting in the effort to come up with
the packages.
It has definitely made designing fixed point circuits much faster and
easier for me
and I'm sure for others aswell who have come across this package.

I will try out the suggestions you mentioned.

And just out of curiosity -- do you have an idea on when the package
will become
an IEEE standard? I'm just asking because it would be great to have my
design
"fully" IEEE complaint..I even started using the numeric_std library
instead of the
popular std_logic_arith which I belive is not an IEEE standard.

Thanks,
Divyang M

 

[David Bishop]

Divyang M wrote:

And just out of curiosity -- do you have an idea on when the package
will become
an IEEE standard? I'm just asking because it would be great to have my
design
"fully" IEEE complaint..I even started using the numeric_std library
instead of the
popular std_logic_arith which I belive is not an IEEE standard.

The plan is this year. LRM editing needs to start soon to get
this off the floor.

 

[David Bishop]

Divyang M wrote:

I was wondering if it is possible (and how) to pipeline operations
(such as mult, add, etc) that I use from the Fixed_pkg library?

I am hoping that this will speed up my system a little.

Two ways to do it.

First, use Pipeline retiming. This is a (farily expensive) option on
most synthesis tools. I use this all the time. Just add some extra
registers after every operation and let the tool do the rest.

Second, create pipelined components of the correct width, and take
the functions apart to use them.

Example:
entity mult_18 is port (
a, b : sfixed (4 downto -4);
res : sfixed (8 downto -8);
clk, rst : std_ulogic);
end entity mult_18;

architecture piplined of mult_18 is
signal as, bs : signed (a'high-a'low downto 0);
signal res_s : signed (2*(a'high-a'low)+1 downto 0);
component pip_signed_mult
..... -- Built with the Wizard
end component;
begin
as <= signed (to_slv (a)); -- cast into a signed numbre
bs <= signed (to_slv (b));
u1 : pip_signed_mult port map (
... -- hook it up
res <= to_sfixed (std_logic_vector(res_s (res_s'high-1 downto 0),
res'high, res'low);
end architecture piplined;

Why does he drop the last bit does he ask? It turns out the the
signed multiply from "numeric_std" gives you one more bit than you
can possibly use.

BTW, I'm the guy who wrote these packages.