Pipelined Architecture ?

[dash82]

Hi,

I am trying to understand what Pipelined designing/architecture for
FPGA's mean ?

I went through documents which list all the benefits of using
pipelining for FPGA's. But, none of them explicitly explained how
pipelined architecture was better (efficiency-wise) against a non-
pipelined architecture. I would'nt generally ask such kind of
questions in a forum. But going through books on Verilog (Samir
Palnitkar's)and searching in Google didnt help me.

It would help me if someone could point to some article (and
preferably a Verilog based one) which explains pipelining at in
depth.

Thanks.

Shah.

 

[Guenter Dannoritzer]

dash82 wrote:

Hi,

I am trying to understand what Pipelined designing/architecture for
FPGA's mean ?

I went through documents which list all the benefits of using
pipelining for FPGA's. But, none of them explicitly explained how
pipelined architecture was better (efficiency-wise) against a non-
pipelined architecture. I would'nt generally ask such kind of
questions in a forum. But going through books on Verilog (Samir
Palnitkar's)and searching in Google didnt help me.

The idea of pipelining is to achieve a higher clock frequency for the
overall synchronous design. Adding pipelining will usually increase the
clock cycles for a certain process, but on the other hand allow to
increase the clock frequency, which in turn will increase the overall
throughput.

So the core issue to understand is, what determines the clock frequency
of the overall design. The clock frequency is determined by the biggest
delay of a combinational logic part. When this delay can be reduced, the
usable clock frequency can be increased.

The way to decrease the delay is by chopping up the combinational logic
part in smaller chunks with synchronous registers in between.

It would help me if someone could point to some article (and
preferably a Verilog based one) which explains pipelining at in
depth.

The problem with some of the HDL books is that they describe the
language from the syntax perspective and leave out the aspect of how
code pieces resemble synthesized. Have a look at books that focus on
implementation with HDL.

One that comes to my mind is:

Wayne Wolf, "FPGA-Based System Design", Prentice Hall 2004.

It explains the FPGA and how Verilog or VHDL code turns out when
implemented on it.

Hope that helps.

Cheers,

Guenter

 

[dash82]

On Nov 27, 4:12 am, Guenter Dannoritzer <kratfkryk...@spammotel.com>
wrote:

dash82 wrote:
Hi,

I am trying to understand what Pipelined designing/architecture for
FPGA's mean ?

I went through documents which list all the benefits of using
pipelining for FPGA's. But, none of them explicitly explained how
pipelined architecture was better (efficiency-wise) against a non-
pipelined architecture. I would'nt generally ask such kind of
questions in a forum. But going through books on Verilog (Samir
Palnitkar's)and searching in Google didnt help me.

The idea of pipelining is to achieve a higher clock frequency for the
overall synchronous design. Adding pipelining will usually increase the
clock cycles for a certain process, but on the other hand allow to
increase the clock frequency, which in turn will increase the overall
throughput.

So the core issue to understand is, what determines the clock frequency
of the overall design. The clock frequency is determined by the biggest
delay of a combinational logic part. When this delay can be reduced, the
usable clock frequency can be increased.

The way to decrease the delay is by chopping up the combinational logic
part in smaller chunks with synchronous registers in between.



It would help me if someone could point to some article (and
preferably a Verilog based one) which explains pipelining at in
depth.

The problem with some of the HDL books is that they describe the
language from the syntax perspective and leave out the aspect of how
code pieces resemble synthesized. Have a look at books that focus on
implementation with HDL.

One that comes to my mind is:

Wayne Wolf, "FPGA-Based System Design", Prentice Hall 2004.

It explains the FPGA and how Verilog or VHDL code turns out when
implemented on it.

Hope that helps.

Cheers,

Guenter

Thank you Guenter !

 

[dash82]

On Nov 29, 11:50 pm, dash82 <dhavalru...@gmail.com> wrote:

On Nov 27, 4:12 am, Guenter Dannoritzer <kratfkryk...@spammotel.com
wrote:



dash82 wrote:
Hi,

I am trying to understand what Pipelined designing/architecture for
FPGA's mean ?

I went through documents which list all the benefits of using
pipelining for FPGA's. But, none of them explicitly explained how
pipelined architecture was better (efficiency-wise) against a non-
pipelined architecture. I would'nt generally ask such kind of
questions in a forum. But going through books on Verilog (Samir
Palnitkar's)and searching in Google didnt help me.

The idea of pipelining is to achieve a higher clock frequency for the
overall synchronous design. Adding pipelining will usually increase the
clock cycles for a certain process, but on the other hand allow to
increase the clock frequency, which in turn will increase the overall
throughput.

So the core issue to understand is, what determines the clock frequency
of the overall design. The clock frequency is determined by the biggest
delay of a combinational logic part. When this delay can be reduced, the
usable clock frequency can be increased.

The way to decrease the delay is by chopping up the combinational logic
part in smaller chunks with synchronous registers in between.

It would help me if someone could point to some article (and
preferably a Verilog based one) which explains pipelining at in
depth.

The problem with some of the HDL books is that they describe the
language from the syntax perspective and leave out the aspect of how
code pieces resemble synthesized. Have a look at books that focus on
implementation with HDL.

One that comes to my mind is:

Wayne Wolf, "FPGA-Based System Design", Prentice Hall 2004.

It explains the FPGA and how Verilog or VHDL code turns out when
implemented on it.

Hope that helps.

Cheers,

Guenter

Thank you Guenter !

Unfortunately, I dont have access to this book. If someone could give
or
point to some other book / example / article, then it would be
helpful.

Thanks.

Shah.