pin placement with SE

L

Luca

Guest
Hi,

I need some help regarding my design flow while using SiliconEnsemble
(version 5.4) for P&R.
I have a small design composed of 8 pins.

Here is a design flow that I followed with SE:
1. Import the LEF (..works)
2. Import verilog. (..works)
3. Import the DEF which contains the pins position. (..works)
4. Floorplan: (..works)
5. Create rings (....works)
6. Place Cells: here is where I get errors
Since I already defined the pins position in the def file. I don't check
the "pins placement" option. This what I get:

SET VAR QPWR.RSPF ""
SET VAR QPLACE.PLACE.GROUTE.ANALYSIS "temp.congMap"
SET VAR QPLACE.OPT.TIMING.TYPE ""
SET VAR QPLACE.PLACE.PIN ""
QPLACE NOCONFIG

..
..
8:49:43 * PLACE : Read in 16 physical pins
8:49:43 * PLACE : 16 physical pins: 8 unplaced, 0 placed, 8 fixed
..
..
..
8:49:43 * PLACE : Pin must be preplaced.
** SE-USER-61 ERROR **
8:49:43 * PLACE : * 8 out of 16 pins are unplaced ... cannot handle !
8:49:43 * PLACE : Please preplace those pins or use placePin option to
get pin locations!
8:49:43 * PLACE : PLACE FAILS


If I check the "pins placement" option, I get no errors but SE place the
pins in different places.

When I import the DEF of my circuit, SE can recognize the pins and I can
see them on the screen.
I there any option or variable to change to indicate that SE must use
the pins defined inthe DEF?

I would appreciate any help on this.

Thanks in advance.
 
On Thu, 10 Feb 2005 09:06:02 +0100, Luca <luca.rossi@unine.ch> wrote:

Hi,

I need some help regarding my design flow while using SiliconEnsemble
(version 5.4) for P&R.
I have a small design composed of 8 pins.

Here is a design flow that I followed with SE:
1. Import the LEF (..works)
2. Import verilog. (..works)
3. Import the DEF which contains the pins position. (..works)
4. Floorplan: (..works)
5. Create rings (....works)
6. Place Cells: here is where I get errors
Since I already defined the pins position in the def file. I don't check
the "pins placement" option. This what I get:

SET VAR QPWR.RSPF ""
SET VAR QPLACE.PLACE.GROUTE.ANALYSIS "temp.congMap"
SET VAR QPLACE.OPT.TIMING.TYPE ""
SET VAR QPLACE.PLACE.PIN ""
QPLACE NOCONFIG

.
.
8:49:43 * PLACE : Read in 16 physical pins
8:49:43 * PLACE : 16 physical pins: 8 unplaced, 0 placed, 8 fixed
.
.
.
8:49:43 * PLACE : Pin must be preplaced.
** SE-USER-61 ERROR **
8:49:43 * PLACE : * 8 out of 16 pins are unplaced ... cannot handle !
8:49:43 * PLACE : Please preplace those pins or use placePin option to
get pin locations!
8:49:43 * PLACE : PLACE FAILS


If I check the "pins placement" option, I get no errors but SE place the
pins in different places.

When I import the DEF of my circuit, SE can recognize the pins and I can
see them on the screen.
I there any option or variable to change to indicate that SE must use
the pins defined inthe DEF?

I would appreciate any help on this.

Thanks in advance.
Click to expand...
are you sure the pins in the def are the same pins in the verilog ?
spelling, case differences maybe ?
one thing to try would be let se place the pins after reading verilog,
def and see if you really have 16 pins and not 8 and where se is
getting the extra 8 pins.
 
You have to also to check that the following variable is set to TRUE :

SET VAR INPUT.VERILOG.CREATE.IO.PINS TRUE ;

================
Kholdoun TORKI
cmp.imag.fr
================

mk wrote:
are you sure the pins in the def are the same pins in the verilog ?
spelling, case differences maybe ?
one thing to try would be let se place the pins after reading verilog,
def and see if you really have 16 pins and not 8 and where se is
getting the extra 8 pins.

On Thu, 10 Feb 2005 09:06:02 +0100, Luca <luca.rossi@unine.ch> wrote:


Hi,

I need some help regarding my design flow while using SiliconEnsemble
(version 5.4) for P&R.
I have a small design composed of 8 pins.

Here is a design flow that I followed with SE:
1. Import the LEF (..works)
2. Import verilog. (..works)
3. Import the DEF which contains the pins position. (..works)
4. Floorplan: (..works)
5. Create rings (....works)
6. Place Cells: here is where I get errors
Since I already defined the pins position in the def file. I don't check
the "pins placement" option. This what I get:

SET VAR QPWR.RSPF ""
SET VAR QPLACE.PLACE.GROUTE.ANALYSIS "temp.congMap"
SET VAR QPLACE.OPT.TIMING.TYPE ""
SET VAR QPLACE.PLACE.PIN ""
QPLACE NOCONFIG

.
.
8:49:43 * PLACE : Read in 16 physical pins
8:49:43 * PLACE : 16 physical pins: 8 unplaced, 0 placed, 8 fixed
.
.
.
8:49:43 * PLACE : Pin must be preplaced.
** SE-USER-61 ERROR **
8:49:43 * PLACE : * 8 out of 16 pins are unplaced ... cannot handle !
8:49:43 * PLACE : Please preplace those pins or use placePin option to
get pin locations!
8:49:43 * PLACE : PLACE FAILS


If I check the "pins placement" option, I get no errors but SE place the
pins in different places.

When I import the DEF of my circuit, SE can recognize the pins and I can
see them on the screen.
I there any option or variable to change to indicate that SE must use
the pins defined inthe DEF?

I would appreciate any help on this.

Thanks in advance.
Click to expand...
 
Kholdoun TORKI wrote:
SET VAR INPUT.VERILOG.CREATE.IO.PINS TRUE ;
Click to expand...
Software that shouts must be BANNED from this group !
Let s blacklist all code from fortran , dracula , silicon ensemble, ...
 
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