pin configuration for I2C on altera Max 10 using i2c_opencor

Hi,

I am using a max 10 FPGA, and trying to communicate with an I2C slave.
I am using the HSMC connector to connect to another board where the I2C slave is located.
I have tested the SDA and SCL lines, so I know they are mapped through the HSMC port correctly. Then I added pullup resistors to the I2C slave PCB, pulling the line to 3.3v. However, when I program the FPGA both SDA and SCL lines get pulled down to 1.9V, so it seems like they are driving against the pullup instead if beeing tri-stated?
I have added OPNDRN primitives to the output pins and according to the synthesis report, the output pins are configures as opendrain. Is there any other type of configuration that needs to be set?

 

[BobH]

On 07/29/2016 01:21 AM, tomberge@gmail.com wrote:

Hi,

I am using a max 10 FPGA, and trying to communicate with an I2C slave.
I am using the HSMC connector to connect to another board where the I2C slave is located.
I have tested the SDA and SCL lines, so I know they are mapped through the HSMC port correctly. Then I added pullup resistors to the I2C slave PCB, pulling the line to 3.3v. However, when I program the FPGA both SDA and SCL lines get pulled down to 1.9V, so it seems like they are driving against the pullup instead if beeing tri-stated?
I have added OPNDRN primitives to the output pins and according to the synthesis report, the output pins are configures as opendrain. Is there any other type of configuration that needs to be set?

Your output structure needs to support it. In Verilog, this works:

tri1 SCL, SDA; // out to pins

// internal use signals
wire SCL_in, SDA_in;
wire SDA_out, SCL_out;

// hookup the pin signals
assign SDA = SDA_out ? 1'bz : 1'b0;
assign SCL = SCL_out ? 1'bz : 1'b0;

// grab the input values
assign SCL_in = SCL;
assign SDA_in = SDA;

 

[Tim Wescott]

On Fri, 29 Jul 2016 01:21:44 -0700, tomberge wrote:

Hi,

I am using a max 10 FPGA, and trying to communicate with an I2C slave.
I am using the HSMC connector to connect to another board where the I2C
slave is located.
I have tested the SDA and SCL lines, so I know they are mapped through
the HSMC port correctly. Then I added pullup resistors to the I2C slave
PCB, pulling the line to 3.3v. However, when I program the FPGA both SDA
and SCL lines get pulled down to 1.9V, so it seems like they are driving
against the pullup instead if beeing tri-stated?
I have added OPNDRN primitives to the output pins and according to the
synthesis report, the output pins are configures as opendrain. Is there
any other type of configuration that needs to be set?

What is powering that output bank? If it's powered by 1.8V, are the pins
compatible with higher supply voltages? 1.9V sounds like an open-drain
output that's powered by 1.8V and isn't 3.3V compatible.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

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