piecewise function

[dilou]

Hi,

I have to implement in VHDL a piecewise linear function but i havent
any idea how i can implement it, have anyone any idea????

 

[Mike Treseler]

dilou wrote:

Hi,

I have to implement in VHDL a piecewise linear function but i havent
any idea how i can implement it, have anyone any idea????

y := m * x + b;


-- Mike Treseler

 

[Mark Norton]

dilou wrote:

Hi,

I have to implement in VHDL a piecewise linear function but i havent
any idea how i can implement it, have anyone any idea????

You haven't exactly given a lot of information, but assuming you have to
take in one number and produce an output based on a piecewise linear
function, you might try something like the following (WARNING:
pseudocode... translate appropriately to VHDL before synthesizing.)

if (inputvalue < first_point) then
outputvalue <= first_region_function();
elsif (inputvalue >= first_point and inputvalue < second_point) then
outputvalue <= second_region_function();
elsif (....
-- continue through all regions of piecewise linear function
.....
else
-- hopefully you've covered all regions, but if not
-- fall through condition here
outputvalue <= some_error_number
end if;

Hope it helps.

Best regards,
Mark Norton


--
==============================
Mark Norton <markn@cdvinc.com>
Concept Development, Inc.
http://www.cdvinc.com

 

[dilou]

I need your help for implementing the pwl in FPGA using VHDL. In a
study I have found this approximation of the sigmoid function:

It can be approximate it at:
y(v) = mi( v-vi-1) + ni-1 , v <> [ vi-1, vi]
ni = mi ( vi - vi-1 ) + ni-1, i=1,2,3,...
with v0=0, n0=0



i : number of sections of the interval of (v) of the function
yi : linear approximation of the function in the section i
mi : slope in the section i
ni : ordered in the origin of section i



It said that the hardware for implementing this version is:
ˇ comparators to determinate the area,
ˇ multipliers,
ˇ the sumator and a set of registers to save the differents valors
of slope and displacement and the mi and ni.

My problem is:

I don't know how can I choose the slope and the interval, also if
this method is best or no?
Mu project is to implement a Hopfield network with the pwl function
instead of the look up table function.

Thanks for your comprehension.

Best Regards,

 

[Mark Norton]

dilou wrote:

I need your help for implementing the pwl in FPGA using VHDL. In a
study I have found this approximation of the sigmoid function:

It can be approximate it at:
y(v) = mi( v-vi-1) + ni-1 , v <> [ vi-1, vi]
ni = mi ( vi - vi-1 ) + ni-1, i=1,2,3,...
with v0=0, n0=0



i : number of sections of the interval of (v) of the function
yi : linear approximation of the function in the section i
mi : slope in the section i
ni : ordered in the origin of section i



It said that the hardware for implementing this version is:
ˇ comparators to determinate the area,
ˇ multipliers,
ˇ the sumator and a set of registers to save the differents valors
of slope and displacement and the mi and ni.

My problem is:

I don't know how can I choose the slope and the interval, also if
this method is best or no?
Mu project is to implement a Hopfield network with the pwl function
instead of the look up table function.

I think you should look at my other reply. A sequence of the sort:
if (value >= v0 and value < v1) then
-- Use region v0 to v1 slope and intercept to calculate
elsif (value >= v1 and value < v2) then
-- Use region v1 to v2 slope and intercept
elsif (...
-- Last region
end if;

will generate comparators to check "value" against the v0, v1, ... vn
numbers and the sections in between you will multiply and add numbers to
get to the output. As far as I can tell, that will generate
comparators, multipliers, and a summation structures.

Apart from this, I don't know what more to tell you. If the syntax
looks unfamiliar, I would advise cracking open a book on VHDL.

Best regards,
Mark Norton

--
==============================
Mark Norton <markn@cdvinc.com>
Concept Development, Inc.
http://www.cdvinc.com