Phase noise plateau

[Andrew Holme]

My hobby project PLL synthesizer has a -70 dBc/Hz phase noise "plateau"
close-in from the carrier out to about 200 Hz.

Wanting to know how nV/sqrt(Hz) on the tuning voltage translate to dBc/Hz, I
did some Googling and found this:

http://www.wirelessdesignmag.com/pdfs/wd35dc.pdf

This article uses the formula:

L(fos)E = 20*log (N * Kv / ((root 2) * fos)) dBc/Hz

where N = noise density, volts/root Hz, fed to VCO tune port
Kv = tuning slope, Hz/V
fos = offset frequency, Hz

Two things -

1. How is this equation derived?
2. Assuming the op-amp noise density is flat, L(fos) falls with increasing
fos - so it could never produce a plateau. Is a phase noise plateau around
the carrier *always* a tell-tale sign of phase comparator and/or reference
noise?


TIA
Andrew.


PS - The vital statistics of my PLL are:

Comparison frequency = 100 KHz
Output frequency = 15.6 MHz (i.e. divider N=156)
-3dB Loop bandwidth ~ 300 Hz
VCO (Mini-Circuits POS-25) tuning sensitivity = 2.58 MHz / Volt
Reference oscillator = 10 MHz DIL-14 xtal module
Phase detector = AD9901-style (XOR gate)
The phase detector, reference and VCO dividers are implemented in an Altera
EPM7128S CPLD.

 

[Andrew Holme]

Andrew Holme wrote:

My hobby project PLL synthesizer has a -70 dBc/Hz phase noise
"plateau" close-in from the carrier out to about 200 Hz.

Wanting to know how nV/sqrt(Hz) on the tuning voltage translate to
dBc/Hz, I did some Googling and found this:

http://www.wirelessdesignmag.com/pdfs/wd35dc.pdf

This article uses the formula:

L(fos)E = 20*log (N * Kv / ((root 2) * fos)) dBc/Hz

where N = noise density, volts/root Hz, fed to VCO tune port
Kv = tuning slope, Hz/V
fos = offset frequency, Hz

Two things -

1. How is this equation derived?
2. Assuming the op-amp noise density is flat, L(fos) falls with
increasing fos - so it could never produce a plateau. Is a phase
noise plateau around the carrier *always* a tell-tale sign of phase
comparator and/or reference noise?

After sleeping on it, a couple of things have dawned on me. Firstly, I can
see the VCO gain k/s in that equation, but I still don't understand how/why
it's possible to get dBc/Hz out from nV/sqrt(Hz) in, like this. Secondly,
I've remembered the loop has a high-pass response to VCO noise, and a low
pass response to noise injected *anywhere* else. So op-amp noise could make
a plateau, right? The noise level I'm seeing just seems a bit high to be
accounted for by the reference multiplied - but I don't know for sure.

PS - The vital statistics of my PLL are:

Comparison frequency = 100 KHz
Output frequency = 15.6 MHz (i.e. divider N=156)
-3dB Loop bandwidth ~ 300 Hz
VCO (Mini-Circuits POS-25) tuning sensitivity = 2.58 MHz / Volt
Reference oscillator = 10 MHz DIL-14 xtal module
Phase detector = AD9901-style (XOR gate)
The phase detector, reference and VCO dividers are implemented in an
Altera EPM7128S CPLD.

 

[Andrew Holme]

Andrew Holme wrote:

Andrew Holme wrote:
My hobby project PLL synthesizer has a -70 dBc/Hz phase noise
"plateau" close-in from the carrier out to about 200 Hz.

Wanting to know how nV/sqrt(Hz) on the tuning voltage translate to
dBc/Hz, I did some Googling and found this:

http://www.wirelessdesignmag.com/pdfs/wd35dc.pdf

This article uses the formula:

L(fos)E = 20*log (N * Kv / ((root 2) * fos)) dBc/Hz

where N = noise density, volts/root Hz, fed to VCO tune port
Kv = tuning slope, Hz/V
fos = offset frequency, Hz

Two things -

1. How is this equation derived?
2. Assuming the op-amp noise density is flat, L(fos) falls with
increasing fos - so it could never produce a plateau. Is a phase
noise plateau around the carrier *always* a tell-tale sign of phase
comparator and/or reference noise?

After sleeping on it, a couple of things have dawned on me. Firstly,
I can see the VCO gain k/s in that equation, but I still don't
understand how/why it's possible to get dBc/Hz out from nV/sqrt(Hz)

In section 2.1 of "Digital PLL frequency synthesizers" Ulrich Rohde derives
the amplitude of NBFM sidebands as thetaP/2 where thetaP = modulation index
= deltaF / fmod where deltaF = max deviation and fmod = modulating freq.

If the peak noise voltage was N, the peak deviation would be deltaF = N*Kvco
Relative sideband amplitude S(fos) = thetaP/2 = N*Kvco / fos / 2
So, I'm almost there, except for the root 2 thing - presumably something to
do with peak/rms?

 

[OBones]

Andrew Holme wrote:

If the peak noise voltage was N, the peak deviation would be deltaF = N*Kvco
Relative sideband amplitude S(fos) = thetaP/2 = N*Kvco / fos / 2
So, I'm almost there, except for the root 2 thing - presumably something to
do with peak/rms?

Well, considering that RMS is a short for Root Mean Square...

 

[John Miles]

In article <d69ip9$gbg$1$8300dec7@news.demon.co.uk>, andrew@nospam.com
says...

Andrew Holme wrote:
2. Assuming the op-amp noise density is flat, L(fos) falls with
increasing fos - so it could never produce a plateau. Is a phase
noise plateau around the carrier *always* a tell-tale sign of phase
comparator and/or reference noise?

In a basic single-loop PLL, yeah, pretty much.

After sleeping on it, a couple of things have dawned on me. Firstly, I can
see the VCO gain k/s in that equation, but I still don't understand how/why
it's possible to get dBc/Hz out from nV/sqrt(Hz) in, like this.

Without having looked at the equations much, my guess is that it's a
consequence of power (which is what 'dBc' ultimately refers to) being
proportional to voltage squared over a given impedance.

I'll confess I usually just rely on what the PFD manufacturers'
simulations tell me when I need a prediction. I haven't tried
homebrewing my own PFD chip (and don't intend to.)

I was sort of hoping one of the more qualified folks would chime in on
your thread, as the question of exactly where your -70 dBc/Hz figure
came from is an interesting one.

Secondly,
I've remembered the loop has a high-pass response to VCO noise, and a low
pass response to noise injected *anywhere* else. So op-amp noise could make
a plateau, right? The noise level I'm seeing just seems a bit high to be
accounted for by the reference multiplied - but I don't know for sure.

I agree; -70 dBc/Hz inband is not optimal for an HF PLL with a clean
reference. How exactly are you measuring it? Are you using a spectrum
analyzer whose synthesizer is noisier than your own? At HF, that's the
rule rather than the exception, since most analyzers use multi-octave
microwave LOs. I have seen people hook an 8563E up to an HP 10811 OCXO
standard and conclude that its phase noise is -116 dBc/Hz at 10 kHz from
the carrier.

Are you remembering to do the 10*log(RBW) thing to turn measured dB into
dBc/Hz? If your equipment does this automatically, did you tell it to
subtract the actual reference level (if not 0 dBm) before calculating
dBc/Hz?

Noise from the opamp is really equivalent to noise internal to the VCO,
if you think about it. A noisy opamp will usually affect the noise
outside the loop bandwidth more than it will raise the height of the
plateau. (Conceptually, where does the opamp's influence end and that
of the VCO's tank circuit begin?)

The PFD can generate a correction signal to counteract noise
contributions from both sources, but only within the loop bandwidth, and
only down to the PFD's own noise-floor limit. The -70 dBc/Hz figure
sounds to me like a measurement error, or a gross problem with the PFD
implementation. None of the loop parameters you mentioned seem out of
line to me.

-- jm

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[Andrew Holme]

John Miles wrote:

In article <d69ip9$gbg$1$8300dec7@news.demon.co.uk>, andrew@nospam.com
says...
Andrew Holme wrote:
2. Assuming the op-amp noise density is flat, L(fos) falls with
increasing fos - so it could never produce a plateau. Is a phase
noise plateau around the carrier *always* a tell-tale sign of phase
comparator and/or reference noise?

In a basic single-loop PLL, yeah, pretty much.

After sleeping on it, a couple of things have dawned on me.
Firstly, I can see the VCO gain k/s in that equation, but I still
don't understand how/why it's possible to get dBc/Hz out from
nV/sqrt(Hz) in, like this.

Without having looked at the equations much, my guess is that it's a
consequence of power (which is what 'dBc' ultimately refers to) being
proportional to voltage squared over a given impedance.

I'll confess I usually just rely on what the PFD manufacturers'
simulations tell me when I need a prediction. I haven't tried
homebrewing my own PFD chip (and don't intend to.)

I was sort of hoping one of the more qualified folks would chime in on
your thread, as the question of exactly where your -70 dBc/Hz figure
came from is an interesting one.

That's what I was hoping for too but I think I may have the answer now
(see below).

Secondly,
I've remembered the loop has a high-pass response to VCO noise, and
a low pass response to noise injected *anywhere* else. So op-amp
noise could make a plateau, right? The noise level I'm seeing just
seems a bit high to be accounted for by the reference multiplied -
but I don't know for sure.

I agree; -70 dBc/Hz inband is not optimal for an HF PLL with a clean
reference. How exactly are you measuring it? Are you using a
spectrum analyzer whose synthesizer is noisier than your own? At HF,
that's the rule rather than the exception, since most analyzers use
multi-octave microwave LOs. I have seen people hook an 8563E up to
an HP 10811 OCXO standard and conclude that its phase noise is -116
dBc/Hz at 10 kHz from the carrier.

Are you remembering to do the 10*log(RBW) thing to turn measured dB
into dBc/Hz? If your equipment does this automatically, did you tell
it to subtract the actual reference level (if not 0 dBm) before
calculating dBc/Hz?

I'm using a Marconi 2382, which is up to the job, and, yes I did the
10*log(RBW) adjustment.

Noise from the opamp is really equivalent to noise internal to the
VCO, if you think about it. A noisy opamp will usually affect the
noise outside the loop bandwidth more than it will raise the height
of the plateau. (Conceptually, where does the opamp's influence end
and that of the VCO's tank circuit begin?)

The PFD can generate a correction signal to counteract noise
contributions from both sources, but only within the loop bandwidth,
and only down to the PFD's own noise-floor limit. The -70 dBc/Hz
figure sounds to me like a measurement error, or a gross problem with
the PFD implementation. None of the loop parameters you mentioned
seem out of line to me.

I'm now pretty sure the close-in phase noise is due to my loop filter
circuit.

This article is very good http://www.micronetics.com/articles/0202mj.pdf
It derives that equation for nV/sqrt(Hz) --> dBc/Hz

With a VCO tuning sensitivity of 2.58 MHz / volt, it only requires a few
nV/sqrt(Hz) to put -75dBc/Hz (my current figure) on the carrier.

Between the op-amp and the VCO, I have an RC pole comprising 1k resistor and
100n capacitor. The thermal noise of this resistor alone accounts
for -82dBc/Hz ! I'm going to swap them for 100 ohm and 1uF. I'm also going
to try an AD797 op-amp which has much lower noise and higher PSRR than the
NE5534 I'm using at the moment. My power supply decoupling isn't that great
on the op-amp at the moment either. Also, I didn't mention in my earlier
posts, but close-in phase noise was even worse until I replaced an OP42FZ
with the NE5534 and put a 100uF decoupling cap on the + input.

I'm not 100% sure about this, but a possible explanation for the plateau is
that:
1. op-amp input noise voltage tends to fall from DC up to (typ) 1KHz (above
that it levels off)
2. My loop's dynamics apply a 40dB/decade rising response to noise injected
at the loop filter output **
3. The nV/sqrt(Hz) --> dBc/Hz formua has fos on the bottom, so it applies a
falling response
The sum total of these three is a flat(ish) close-in noise level.

** Put a summer at the loop filter output. The output of the summer is the
tuning voltage vt. Inject noise thetaN into the summer. Do a Bode plot of
vt/thetaN and it's a high-pass, rising at 40dB per decade, and then 0dB
above the loop natural frequency.

 

[Andrew Holme]

Mark wrote:

Below the loop BW, the output phase noise will be determined by the
reference, this includes the reference itself (which should be very
clean in your case) and both the ref and var dividers and phase
detector. The noise floor for dividers is about -140 dBc/Hz and is
multiplied by N

Correction: below the loop BW the output phase noise *should* be determined
by the reference - unless some idiot has put a really noisy loop filter in
there (see my other post).

Above the loop BW the phase noise will be the VCO and op amp (less
whatever filtering there is after the op amp)

You can confirm your diagnosis by temporarily changing the loop BW and
see what happens to the phase noise.

What is the phase noise for the VCO POS-25 alone at 200 Hz offset?

Unfortunately, Mini-Circuits only specify it at 1, 10 and 100 KHz.

They quote -86dBc/Hz at 1 KHz.

Since your loop BW is 300 Hz your output phase noise at 200 Hz can be
only a little better than the POS-25 itself is. The phase noise of
the VCO will be increasing as you go lower in frequency. But the
loop gain will also be increasing as you go lower in frequency.
These effects cancel giving you the plateau. Above the loop BW, the
phase noise follows the VCO down. Going down , the plateau remains
flat until the reference noise starts to rise and the output noise
follows it up.

I disagree with you here:
Firstly, 200 Hz is well inside loop BW and therefore under the control of
the loop.
Secondly, the usual cause of the plateau is not that loop gain and VCO phase
noise balance one another. It is - as you said earlier - that phase noise
inside loop BW *should* be that of the reference multiplied; and reference
phase noise is flat except at very small offsets.

Get a copy of the MiniCkts VCO Designers Handbook

I have the Designer's Handbook

Mark

 

[John Miles]

In article <d6dc5s$g2u$1$830fa79f@news.demon.co.uk>, andrew@nospam.com
says...

Mark wrote:
Below the loop BW, the output phase noise will be determined by the
reference, this includes the reference itself (which should be very
clean in your case) and both the ref and var dividers and phase
detector. The noise floor for dividers is about -140 dBc/Hz and is
multiplied by N


Correction: below the loop BW the output phase noise *should* be determined
by the reference - unless some idiot has put a really noisy loop filter in
there (see my other post).

It'll definitely be interesting if you can post what happens with the
smaller resistor value and quieter op-amp. My gut feel is that it won't
make much difference to the noise inside the loop bandwidth, since the
opamp and filter are inside the loop just like the VCO varactor is. But
it sounds like you've already seen some results that suggest otherwise.

My current favorite PLL opamp is the LT1677. It is basically an OPA27
clone but it has true rail-to-rail capability and better CMRR/PSRR.
Nice part when you need to drive a higher-voltage VCO.

-- jm

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[Mike Monett]

John Miles wrote:

[...]

My current favorite PLL opamp is the LT1677. It is basically an OPA27
clone but it has true rail-to-rail capability and better CMRR/PSRR.
Nice part when you need to drive a higher-voltage VCO.

-- jm

John, thanks for the info on the LT1677.

A bit off topic, but did you see Design Note 230? It shows a neat
trick on how to make a differential amplifier with high common mode
range without sacrificing gain. Here's the description:

--------------------------------------------------------------------
"Measuring small voltages on top of large voltages can be quite
difficult. Often, the standard difference amplifier topology is
implemented with very high value input resistors and low value
divide and feedback resistors, as shown in Figure 2. However, this
results in significant differential mode attenuation."

"The circuit in Figure 3 uses an LT1884 to achieve high common
mode input range and rejection without sacrificing differential
gain."
--------------------------------------------------------------------

Here's the url for DN230.PDF. You may have to rename while saving:

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1099,P1834,D4448

Here's a shorter version in case the above doesn't work in your
browser:

http://tinyurl.com/dm57p

Mike Monett

 

[John Miles]

In article <428A53ED.7BB7@spam.com>, no@spam.com says...

Here's the url for DN230.PDF. You may have to rename while saving:

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1099,P1834,D4448

Here's a shorter version in case the above doesn't work in your
browser:

http://tinyurl.com/dm57p

Mike Monett

Yeah, those are both neat apps. I like the idea of sending an analog
signal back through a bridge-rectified supply line as a modulated
current. One of those things that are obvious when someone else does
it...

-- jm

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[John Miles]

In article <1116509280.304560.147980@g43g2000cwa.googlegroups.com>,
ajholme@hotmail.com says...

Originally, the PLL was much noisier. I got 10dB improvement by
altering the VCO buffer/limiter, and 10dB cleaning up the loop filter;
however, there was no further improvement with the 100 ohm resistor,
and only a dB or 2 for the AD797.

I'm not too surprised. Again, there is no magic place where your VCO's
noise contribution stops and the opamp's begins. Control-wise, it looks
like one big varactor-tuned tank circuit driven by a phase detector.
Sure, there are one or more additional poles, but I don't see a reason
why their exact position in the circuit should make any difference, as
long as the loop isn't way underdamped. (Meaning, as long as it
actually has the gain needed to establish dominance over the spectral
content within the loop bandwidth as defined by the lowest-frequency
pole).

Annoyingly, the 797 doesn't like acquiring lock, but I managed to
persuade it for the purpose of the test! I see it has a differential
input resistance of only 7.5k, which may be upsetting my loop filter.

Well, that, or the XOR type phase detector. If you switch to a true
PFD, your acquisition problems may go away.

An ideal opamp for PLL work would have no input bias current and no
noise. It wouldn't load the phase detector (or its charge pump) at all.
(It would also, as an app note I saw the other day suggests, cost $0.00
in quantities of 10 and up.

That's for later...

Next, following suggestions made in another thread, I'm going to
replace my rather dubious VCO buffer / limiter with a couple of HCU04
gates. If I can just get it down another 10dB, I'll be satisfied.

I know you got some good advice from Win Hill and some other folks on
that, and I'm far from qualified to debate it with them, but I really am
not a fan of (mis)using HC TTL gates as buffers. You want a buffer, use
a buffer chip or a diff amp. The microwave guys in the Amateur
community have been having all sorts of fits with a popular reference-
lock board lately because a 'clever' TTL buffer application proved
dependent on chips from one particular manufacturer. That's not the
first time I've heard of circuits coming to grief that way.

When I need to drive a TTL counter or something, I usually just use a
grounded-emitter bipolar with 10K resistors on either side of the base
and a 680-ohm collector load resistor to +5. The analog signal comes in
through a 0.1 uF capacitor to the base. A 10-20 MHz input signal is
fine down to -10 dBm or so with an ordinary 2N2222, and you get a signal
at the collector that can drive TTL directly.

It would probably earn a place on one of Win's famous "BAD!" circuit
pages for one reason or another, but, hey, it survived at least one
design review at Tektronix... and it's not going to break when someone
decides to make their 2N2222s a little bit differently.

-- jm

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[Andrew Holme]

Andrew Holme wrote:

John Miles wrote:
[snip]

John,

I've re-designed the loop filter for wider bandwidth, using small resistors,
and the close-in phase noise is now down to -86dBc/Hz rising to a peak
of -82dBc/Hz at a 500Hz offset. This agrees with a SCILAB design prediction
of a 4dB peaking in closed-loop response. Now that I actually have some
loop gain at 50 Hz to reject line frequency, I no longer have to operate the
PLL in a screened box to see this performance! I'm thrilled. Thanks for
triggering the eureka moment earlier. The problem was simply a lack of loop
gain. I can't believe I was so dumb not to realise it.

Andrew.

 

[John Miles]

In article <d6lhc7$d85$1$8300dec7@news.demon.co.uk>, andrew@nospam.com
says...

Andrew Holme wrote:
John Miles wrote:
[snip]

John,

I've re-designed the loop filter for wider bandwidth, using small resistors,
and the close-in phase noise is now down to -86dBc/Hz rising to a peak
of -82dBc/Hz at a 500Hz offset. This agrees with a SCILAB design prediction
of a 4dB peaking in closed-loop response. Now that I actually have some
loop gain at 50 Hz to reject line frequency, I no longer have to operate the
PLL in a screened box to see this performance! I'm thrilled. Thanks for
triggering the eureka moment earlier. The problem was simply a lack of loop
gain. I can't believe I was so dumb not to realise it.

Andrew.

Neat! Sounds like the loop was still getting quieter at the 200 Hz
offset where you measured it. The smaller resistances and quieter opamp
should still pay off at wider offsets, so they're more than worthwhile.

-- jm

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[John Miles]

In article <1116581843.944808.174140@g44g2000cwa.googlegroups.com>,
ajholme@hotmail.com says...

John Miles wrote:
I know you got some good advice from Win Hill and some other folks on

that, and I'm far from qualified to debate it with them, but I really
am
not a fan of (mis)using HC TTL gates as buffers. You want a buffer,
use
a buffer chip or a diff amp. The microwave guys in the Amateur
community have been having all sorts of fits with a popular
reference-
lock board lately because a 'clever' TTL buffer application proved
dependent on chips from one particular manufacturer. That's not the
first time I've heard of circuits coming to grief that way.

Did they use HCU i.e. un-buffered gates?

Actually I was wrong about that. Luis didn't use an HC part like we
were talking about, but rather an 'F' part:

http://gref.cfn.ist.utl.pt/cupido/ref_sch.pdf

He and another fellow have since designed a newer reflock circuit that
uses a differential pair for input conditioning:

http://gref.cfn.ist.utl.pt/cupido/r2_sch_rev_c.pdf (see page 2)

So I withdraw my uninformed objection to the 74HCU04. I still wouldn't
use one for this purpose myself, but I can't cite any cases offhand
where they've caused trouble.

-- jm

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[Andrew Holme]

John Miles wrote:

In article <1116581843.944808.174140@g44g2000cwa.googlegroups.com>,
ajholme@hotmail.com says...

John Miles wrote:
I know you got some good advice from Win Hill and some other folks
on

that, and I'm far from qualified to debate it with them, but I
really am not a fan of (mis)using HC TTL gates as buffers. You
want a buffer, use a buffer chip or a diff amp. The microwave guys
in the Amateur community have been having all sorts of fits with a
popular reference- lock board lately because a 'clever' TTL buffer
application proved dependent on chips from one particular
manufacturer. That's not the first time I've heard of circuits
coming to grief that way.

Did they use HCU i.e. un-buffered gates?

Actually I was wrong about that. Luis didn't use an HC part like we
were talking about, but rather an 'F' part:

http://gref.cfn.ist.utl.pt/cupido/ref_sch.pdf

He and another fellow have since designed a newer reflock circuit that
uses a differential pair for input conditioning:

http://gref.cfn.ist.utl.pt/cupido/r2_sch_rev_c.pdf (see page 2)

I see they're using CPLDs in those designs

I couldn't tell if the second design is also meant for use up to 150 MHz
with the BFT92 diff pair.

I didn't have much luck with my diff pair, using surplus BF679S devices (ft
~ 1 GHz) of dubious origin. Coincidentally, I've got an unopened pack of
BFT93 here (ordered at the same time as the AD797) which I might try.