Phase / frequency detector types

[Jay]

Hi all.

I am attempting to design an All-Digital Phase Lock Loop for a motor
control application. I know it's been done before, and I might even find
an off the shelf part that does close to what I want, but some
particular requirements force me to use a CPLD/FPGA.

Anyway, I've seen several phase-detector/frequency-detector circuits and
often see "Type I" or "Type IV". Is there any comprehensive list of
phase/frequency detectors and/or advantages/disadvantages? I've Googled
but I'm looking for some engineering insight from the people who've
"been there, done that".

Essentially, what I think I need from the phase/frequency detector are
UP/DOWN signals to tell my system to get the counter-based NCO to run
slower or faster. Are these typically called "bang-bang" type?

Thanks for your help!
Jay.

 

[Peter Alfke]

The issue with phase/frequamcy comparators is that they must work and
correct the error under all circumstances, with both frequencies widely
different, and also with identical frequenceis, but a small phase
difference. That limits the playing field.
Many decades ago, Motorola created a circuit (I think it was calle 4044
or something like it) that did this job beautifully.
I once converted this design into FPGA land, see
http://www.xilinx.com/xapp/xapp028.pdf.

What you do with the bang-bang outputs is up to you. You can integrate
them and feed a VCO, or control an up-down counter...

Peter Alfke, Xilinx
============
Jay wrote:

Hi all.

I am attempting to design an All-Digital Phase Lock Loop for a motor
control application. I know it's been done before, and I might even find
an off the shelf part that does close to what I want, but some
particular requirements force me to use a CPLD/FPGA.

Anyway, I've seen several phase-detector/frequency-detector circuits and
often see "Type I" or "Type IV". Is there any comprehensive list of
phase/frequency detectors and/or advantages/disadvantages? I've Googled
but I'm looking for some engineering insight from the people who've
"been there, done that".

Essentially, what I think I need from the phase/frequency detector are
UP/DOWN signals to tell my system to get the counter-based NCO to run
slower or faster. Are these typically called "bang-bang" type?

Thanks for your help!
Jay.

 

[Symon]

Hi,
A small note of caution when using Peter's XAPP028 in Virtex II. As
well as constraining the logic to the CLBs shown in the app note, make
sure you specify a MAXSKEW attribute on the reference signal and
feedback signal to the circuit. I use 100ps. Without this the circuit
can occasionally malfunction depending on the place and route. (These
are the signals called 'from VCO divided by N' and 'from reference
frequency'.)
There was no problem when this circuit was used on older FPGAs
where the routing to the F and G lookup tables in a single CLB was
guaranteed to have low skew. In Virtex II this is no longer the case
and a single signal that goes to both the F and G inputs of a CLB can
have significant skew if not constrained. This can cause the circuit
of XAPP28 to misbehave.
Of course it's not your fault Peter that those guys changed the
routing from the original 3000 (I guess) design! Thanks for a good APP
note I've used many times, maybe it needs a small update!
HTH, Syms.
p.s. I'm not sure which Xilinx families need the MAXSKEW, I use it
always because it can't hurt. Also, make sure the signals don't
connect anywhere else, or the MAXSKEW will fail. Replicate them if
necessary.


Peter Alfke <peter@xilinx.com> wrote in message news:<3F19DFA5.FA39F53B@xilinx.com>...

The issue with phase/frequamcy comparators is that they must work and
correct the error under all circumstances, with both frequencies widely
different, and also with identical frequenceis, but a small phase
difference. That limits the playing field.
Many decades ago, Motorola created a circuit (I think it was calle 4044
or something like it) that did this job beautifully.
I once converted this design into FPGA land, see
http://www.xilinx.com/xapp/xapp028.pdf.

What you do with the bang-bang outputs is up to you. You can integrate
them and feed a VCO, or control an up-down counter...

Peter Alfke, Xilinx
============
Jay wrote:

Hi all.

I am attempting to design an All-Digital Phase Lock Loop for a motor
control application. I know it's been done before, and I might even find
an off the shelf part that does close to what I want, but some
particular requirements force me to use a CPLD/FPGA.

Anyway, I've seen several phase-detector/frequency-detector circuits and
often see "Type I" or "Type IV". Is there any comprehensive list of
phase/frequency detectors and/or advantages/disadvantages? I've Googled
but I'm looking for some engineering insight from the people who've
"been there, done that".

Essentially, what I think I need from the phase/frequency detector are
UP/DOWN signals to tell my system to get the counter-based NCO to run
slower or faster. Are these typically called "bang-bang" type?

Thanks for your help!
Jay.

 

[Peter Alfke]

The sins of the past...
I patented that method 26 years ago, while I was at Fairchild Semiconductor:
US patent # 4 023 116,
filed July 76, issued May 77.

It's a neat way to reduce jitter when perfect phase adjustment is not required.
Peter Alfke
==========================================
Jim Granville wrote:

If you are seriously worried about PLL/VCO sidebands, better PLL
detectors
have deliberate dead-band removal - this is extra logic that prevents
a 'flat spot' in the phase/voltage curve, that can occur in simpler
digital-state only designs.
If in this class, you should use the FPGA OP to drive an analog switch,
so the relatively noisy Vcc/Gnds do not appear on the VCO control
voltage
domain.

-jg

 

[Symon]

Hi,
Try https://www.national.com/appinfo/wireless/files/DeansBook_4_01.pdf
for a good read on PLLs. I'm thinking of using the design in chapter
12 with the XAPP0028 circuit minus the tri-states.
Also, see XAPP250 for a similar PFD design. In XAPP250 use a delay
between the 'AND' gate and the reset of the FFs to get rid of dead
band. This delay allows both 'up' and 'down' to be on at once, so
don't connect them together without a resistor at least!
HTH, SYms.

Peter Alfke <peter@xilinx.com> wrote in message news:<3F1C202D.8E41AA9@xilinx.com>...

The sins of the past...
I patented that method 26 years ago, while I was at Fairchild Semiconductor:
US patent # 4 023 116,
filed July 76, issued May 77.

It's a neat way to reduce jitter when perfect phase adjustment is not required.
Peter Alfke
==========================================
Jim Granville wrote:

If you are seriously worried about PLL/VCO sidebands, better PLL
detectors
have deliberate dead-band removal - this is extra logic that prevents
a 'flat spot' in the phase/voltage curve, that can occur in simpler
digital-state only designs.
If in this class, you should use the FPGA OP to drive an analog switch,
so the relatively noisy Vcc/Gnds do not appear on the VCO control
voltage
domain.

-jg

 

[Jerry Avins]

Symon wrote:

Hi,
Try https://www.national.com/appinfo/wireless/files/DeansBook_4_01.pdf
for a good read on PLLs. I'm thinking of using the design in chapter
12 with the XAPP0028 circuit minus the tri-states.
...

In most hardware designs, tri state is a way to lock a steady charge on
the integrating cap, instead of always ramping it up or down, "galloping
ghost" style. Applied that way, it reduces phase jitter.

Jerry
--
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ

 

[Symon]

Hi Jerry,
I agree! The circuit in 'Dean's Book' I referred to doesn't use
tri-states, it uses a diff amp integrator driven by the signals that
would've driven the tri-states. This also prevents "galloping ghost",
if I understand your terminology right!? As I learned from the 'book'
this fixes (or can fix) problems with charge leakage from the
tri-state, power supply noise on the tri-state drivers. It also means
the spurs resulting because, typically, the integrated voltage isn't
midway between the rails of the tri-state driver, are lower and more
predictable.
Syms.


Jerry Avins <jya@ieee.org> wrote in message news:<3F1C7F5F.F94678C2@ieee.org>...

Symon wrote:

Hi,
Try https://www.national.com/appinfo/wireless/files/DeansBook_4_01.pdf
for a good read on PLLs. I'm thinking of using the design in chapter
12 with the XAPP0028 circuit minus the tri-states.
...

In most hardware designs, tri state is a way to lock a steady charge on
the integrating cap, instead of always ramping it up or down, "galloping
ghost" style. Applied that way, it reduces phase jitter.

Jerry

 

[Peter Alfke]

If you worry about undefined 3-state levels, you can drive the pin with
either a 50% voltage divider or even from an external source with the
appropriate voltage. Since the active outputs have an impedance far
below 100 Ohm (often around 10 Ohm), there is ample room for creativity.

Peter Alfke
================
Symon wrote:

Hi Jerry,
I agree! The circuit in 'Dean's Book' I referred to doesn't use
tri-states, it uses a diff amp integrator driven by the signals that
would've driven the tri-states. This also prevents "galloping ghost",
if I understand your terminology right!? As I learned from the 'book'
this fixes (or can fix) problems with charge leakage from the
tri-state, power supply noise on the tri-state drivers. It also means
the spurs resulting because, typically, the integrated voltage isn't
midway between the rails of the tri-state driver, are lower and more
predictable.
Syms.

Jerry Avins <jya@ieee.org> wrote in message news:<3F1C7F5F.F94678C2@ieee.org>...
Symon wrote:

Hi,
Try https://www.national.com/appinfo/wireless/files/DeansBook_4_01.pdf
for a good read on PLLs. I'm thinking of using the design in chapter
12 with the XAPP0028 circuit minus the tri-states.
...

In most hardware designs, tri state is a way to lock a steady charge on
the integrating cap, instead of always ramping it up or down, "galloping
ghost" style. Applied that way, it reduces phase jitter.

Jerry