Phase detector for DLL

[Massi]

Hi ,

I am new programmer in VHDL and i have to realize a DLL in an ACTEL
ProASIC board.

I am using Libero 4.6 and Model Sim 5.6b.

I have decided to use as example the 74HC297.

I am having problems to implement a Edge Controlled phase detector
using a simple SRlatch!(not a doubble SRlatch!)

CAn anyone tell me why I got this message on ModelSim:
"Iteration limit reached. Possible zero delay oscillation. See the
manual."

Is not possible to instatiate a simple Latch on Fpga?

I am sure to instante a latch because I have veruified on the netlist
in Synplify! and on the Designer netlist a Dlatch has been
implemented!

Is it only a problem in the use of a Simulator?

Furthermore I am trying to simulate a simple Dlatch with asyncronous
clear with the following testbench:
1) D imput line a signal that represent the frequency I want to lock.
2) Clear input a signal that is opposite to D that represent the
frequency that come from the DCO(to "simulate" a phase detector in the
case when I am in Lock state )


Thanks for any help! and tips you can suggest!


Massimo

 

[Andy Peters]

maxaudrito@yahoo.com (Massi) wrote in message news:<abeb94d1.0401300734.68deedbf@posting.google.com>...

Hi ,

I am new programmer in VHDL and i have to realize a DLL in an ACTEL
ProASIC board.

I am using Libero 4.6 and Model Sim 5.6b.

I have decided to use as example the 74HC297.

I am having problems to implement a Edge Controlled phase detector
using a simple SRlatch!(not a doubble SRlatch!)

CAn anyone tell me why I got this message on ModelSim:
"Iteration limit reached. Possible zero delay oscillation. See the
manual."

Is not possible to instatiate a simple Latch on Fpga?

I am sure to instante a latch because I have veruified on the netlist
in Synplify! and on the Designer netlist a Dlatch has been
implemented!

Is it only a problem in the use of a Simulator?

Furthermore I am trying to simulate a simple Dlatch with asyncronous
clear with the following testbench:
1) D imput line a signal that represent the frequency I want to lock.
2) Clear input a signal that is opposite to D that represent the
frequency that come from the DCO(to "simulate" a phase detector in the
case when I am in Lock state )

Perhaps you can post your code in the appropriate forum: comp.lang.vhdl.

--a

 

[Anders Hellerup Madsen]

Massi wrote:

CAn anyone tell me why I got this message on ModelSim:
"Iteration limit reached. Possible zero delay oscillation. See the
manual."

I think it is a problem with sensitivity lists. At least that's where I
have seen this error. What happens is that the you have listet one of a
process' output signals in the sensitivity list, so that when the
process runs, it causes itself to run again. In theory this causes an
infinete loop, but the simulator protects you against this by having an
iteration limit.

Is not possible to instatiate a simple Latch on Fpga?

Try this:

process(clk, reset)
begin
if (reset = '0') then
d_out <= '0';
elsif (rising_edge(clk) then
d_out <= d_in;
end if;
end proces;

I am sure to instante a latch because I have veruified on the netlist
in Synplify! and on the Designer netlist a Dlatch has been
implemented!

Is it only a problem in the use of a Simulator?

It may be, but it sort of sounds like you are doing something like
implementing the latch with and gates and stuff, like you would in a
schematic program, at the most basic level. This is not the best way to
do it.

-- Anders