J
John Wilkinson
Guest
Hi,
I am trying to design a PLL using the 74HCT7046 chip.
I am using the Phase frequency detector and feeding this into a single
supply op-amp active PI filter. This has its non-inv input tied at
vdd/2=2.5V whilst the amp is on +15V to give the VCO tuning voltage
+2-+15V for a 5MHz change in frequency.
Now what is the gain of the PD. I have reckoned it as 3*vdd/2pi, is this
correct?
Do I need to take into account that the non-inv input is at half VDD?
Has anyone got a schematic for a TTL PFD feeding a fast totem pole type
discrete output at +15V, to up the voltage swing?
Thanks,
John.
I am trying to design a PLL using the 74HCT7046 chip.
I am using the Phase frequency detector and feeding this into a single
supply op-amp active PI filter. This has its non-inv input tied at
vdd/2=2.5V whilst the amp is on +15V to give the VCO tuning voltage
+2-+15V for a 5MHz change in frequency.
Now what is the gain of the PD. I have reckoned it as 3*vdd/2pi, is this
correct?
Do I need to take into account that the non-inv input is at half VDD?
Has anyone got a schematic for a TTL PFD feeding a fast totem pole type
discrete output at +15V, to up the voltage swing?
Thanks,
John.