Ph.inisheD.

[Nicholas C. Weaver]

Well, I FINALLY finished my PhD.

For those who are exceedingly bored, my dissrtation is online (The
SFRA: A Fixed-Frequency FPGA Architecture) at
http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf

--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[rickman]

"Nicholas C. Weaver" wrote:

Well, I FINALLY finished my PhD.

For those who are exceedingly bored, my dissrtation is online (The
SFRA: A Fixed-Frequency FPGA Architecture) at
http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf

Congrats... I am sure it was a lot of work.

Since you are in that lofty group and must have a much better view than
the rest of us, are you aware of much research in FPGAs about
partial/modular configuration?

Just curious.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Nicholas C. Weaver]

In article <3F8DA93C.C2C16FF3@yahoo.com>,
rickman <spamgoeshere4@yahoo.com> wrote:

Since you are in that lofty group and must have a much better view than
the rest of us, are you aware of much research in FPGAs about
partial/modular configuration?

Quick coredump from memory.


There was a lot of stuff on the old 6200 a few years back, because it
was relatively friendly for it. Satnam had some stuff, among others.

Also there was the many-years-back time-multiplexed 4K Xilinx research
project, which virtualized circuits with fine-grained multiplexing
(project never went anywhere because of the power consumption of
context switching every cycle).


There's some on programming model to allow virtualization (eg, SCORE
here at berkeley), these target abstract FPGAs, not current silicon.



There's a lot of interest today internally in Xilinx and elsewhere on
the possibility, but not sure HOW much research is going on, and in
many ways limited by both the silicon (can only reconfigure
column-at-a-time, a feature largely for testing not user design) and
the tools (how do you swap out bits? Represent the swapping? Etc?).

I think if there is some conceptual breakthrough on how to treat the
silicon, the other stuff will probably fall into place, as the
detailed routing (eg, insuring modules don't interfear etc) could be
faked up with Jbits (do a ripup and reroute, and run things 10% slower
to give a margin for simplicity), and "make this change and now these
things run a lot faster" on the silicon could happen in later
egnerations.

But I think its largely awaiting the conceptual breakthrough. How do
you treat this blob which is different things at different points in
time?
--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[Vinh Pham]

Well, I FINALLY finished my PhD.

Congratulations! Sounds like you didn't have the luxary to concentrate
solely on your PhD. You had to juggle a job and perhaps a family also?

How was your dissertation defense? What was the topic?

Congrats again, I'm sure you're glad to have it done with. Now you get to
bust your butt getting tenure, if that's your route ;_)


--Vinh

 

[Ray Andraka]

I have the impression that partial reconfig is sort of dying on the vine.
Tools for it are far from ready for prime time, and the devices have been
growing fast enough that the added development cost to implement partial
reconfig generally outweighs the cost savings achieved for all but the
highest volume designs. I'd done a number of designs that took advantage
of reconfig several years back, but now am not seeing much call for it.

rickman wrote:

"Nicholas C. Weaver" wrote:

Well, I FINALLY finished my PhD.

For those who are exceedingly bored, my dissrtation is online (The
SFRA: A Fixed-Frequency FPGA Architecture) at
http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf

Congrats... I am sure it was a lot of work.

Since you are in that lofty group and must have a much better view than
the rest of us, are you aware of much research in FPGAs about
partial/modular configuration?

Just curious.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Nicholas C. Weaver]

In article <mdnjb.16916$ZH4.13630@twister.socal.rr.com>,
Vinh Pham <a@a.a> wrote:

Congratulations! Sounds like you didn't have the luxary to concentrate
solely on your PhD. You had to juggle a job and perhaps a family also?

Nope. Just had to juggle with interesting distractions like Internet
Worms and the like.

How was your dissertation defense? What was the topic?

Berkeley believes "The best defense is a good offense", I did my
thesis offense (qualifying exam) about 2 years ago.

Congrats again, I'm sure you're glad to have it done with. Now you get to
bust your butt getting tenure, if that's your route ;_)

Tell me about it! Worse, Darpa is NOT funding security work, at least
unclassified security work.
--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[Mike Treseler]

Nicholas C. Weaver wrote:

Tell me about it! Worse, Darpa is NOT funding security work, at least
unclassified security work.

I expect that banks, brokers and amazon.com are.


-- Mike Treseler

 

[JoeG]

Nicholas C. Weaver wrote:

Well, I FINALLY finished my PhD.

For those who are exceedingly bored, my dissrtation is online (The
SFRA: A Fixed-Frequency FPGA Architecture) at
http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf

Congrats -- read the TOC, final conclusion and bibliography . Job well done!


JoeG