Persistent variable in Veriloga in "analog" mode?

Please can someone advise me:
The problem is a standard one [hopefully].
You need a value at “t+1” that is a function of its “t’s” value.

QUESTION:
Is there an equivalent to ‘reg’ to store a state or
Persistent value when in the "analog" mode?

Best wishes
Richard

 

[Cary R.]

On 8/13/2012 5:05 AM, r.neville@manchester.ac.uk wrote:

Please can someone advise me:
The problem is a standard one [hopefully].
You need a value at “t+1” that is a function of its “t’s” value.

QUESTION:
Is there an equivalent to ‘reg’ to store a state or
Persistent value when in the "analog" mode?

Best wishes
Richard

Yes Verilog-A has some support for persistent variables. An integer (32
bit) variable declaration is allowed in an analog context and defaults
to 0 instead of x like it would in a digital context. I believe and it
makes intuitive sense that x/z are not supported in an analog context.
Real variables are also supported and default to 0.0 no matter the
context. Both of these can be arrayed (1-dimension) in an analog context
and support initialization (including Verilog-A array initialization).

FYI using variables will preclude the use of PSS analysis.

Cary