Perl + Xilinx + commandline = Module::Build::Xilinx

V

vicash

Guest
Hello

I have released Module::Build::Xilinx (currently at version 0.05) to CPAN. (https://metacpan.org/pod/Module::Build::Xilinx)

This is a tool that you can use to create a simple makefile like Build.PL script such as done by standard perl modules.

Module::Build::Xilinx subclasses Module::Build to create, build, simulate, view and program Xilinx FPGA development boards by using Perl to manage the Xilinx ISE environment.

You can now do all of this from the commandline and create a lot of required files automatically by typing a couple of commands on the command line.

For example, to create a new project from existing source code with VHDL files in the following tree structure:

--+Build.PL
--+src/toplevel.vhd (and any number of other VHDL files in sub-directories)
--+tb/testbench.vhd (and any number of testbenches)

You will just have to write the following:

$ perl ./Build.PL

The above will create the custom Build file for your project which can be used as below to build a bitstream:

$ ./Build pbuild

This will build the bitstream as expected using the installed Xilinx ISE software.

To run a simulation of a testbench you can do:

$ ./Build simulate

This will use Xilinx's fuse to create a testbench EXE and executes it.

To view the output using ISimGUI you run

$ ./Build view

To program an FPGA device using iMPACT you do:

$ ./Build program --device=/dev/mydevice

The software works the same way on both Windows and Linux. On Windows, I recommend using Strawberry Perl or similar to run Perl and not Cygwin.

More details such as examples and detailed documentation can be seen at :
https://metacpan.org/pod/Module::Build::Xilinx

As time progresses and if there is a demand, I will add Verilog support which may be trivial to add to the software.

Please let me know if you end up using it and if you have issues or feature suggestions. Please email me at the email below for issue/bug-reports.

Thanks
vicash (vikas_AT_cpan.org) (replace _AT_ with @)
 
In addition to this Xilinx ISE 13.x has been thoroughly tested and if you have Xilinx Vivado or a higher version please try and let me know.

Thanks
vikas (vikas_AT_cpan.org)(replace _AT_ with @)
 
Any plan to support Verilog or mixed language projects?

Yes I do have a plan. If you have a sample example that you can provide for each that does something really simple like a flip-flop or register then I can use that as a basis for testing and development. Supporting Verilog should just be a matter of minutes if not a couple of hours.

I am a novice VHDL programmer and do not do any Verilog yet.

--vicash
 
vicash wrote:
In addition to this Xilinx ISE 13.x has been thoroughly tested and if you have Xilinx Vivado or a higher version please try and let me know.

Thanks
vikas (vikas_AT_cpan.org)(replace _AT_ with @)

On the web page I see:

The language supported in the project is VHDL. We do not yet support
Verilog.

Any plan to support Verilog or mixed language projects?

--
Gabor
 
On Tuesday, July 8, 2014 4:59:01 PM UTC-4, Gabor wrote:
Any plan to support Verilog or mixed language projects?

Version 0.06 has been released to CPAN with Verilog and Mixed HDL (VHDL + Verilog) support.
 

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