Guest
Hey Gentlemen,
I was wondering if there is a way to encapsulate Perl code in a
Verilog module so that on compilation ncverilog can expand on it. I'm
doing RTL for very large components and generate a lot of the code in
perl with small scripts. Is there a way to write part of the script in
the module itself to make it more readable and have ncverilog expand
on it?
Thanks!
I was wondering if there is a way to encapsulate Perl code in a
Verilog module so that on compilation ncverilog can expand on it. I'm
doing RTL for very large components and generate a lot of the code in
perl with small scripts. Is there a way to write part of the script in
the module itself to make it more readable and have ncverilog expand
on it?
Thanks!