Periodic waveform creation?

[JeffC]

I'm a Verilog newbie of about a week (I know, they are everywhere). I'm
trying to generate four synchronized periodic digital waveforms (they
are not square or PWM) for output from my Spartan 3 FPGA. I'm wondering
the best way to go about this. In the past I used sequential vectors of
digital values to represent how the logic levels progress in time (with
an 8 port PIC micro controller). Now I need more flexibility and
features which is why I'm up to FPGAs. I thought perhaps an always
block along these lines (for a simple square wave)...



module waveforms(clk, linesout);

input clk;
output [3:0] linesout;
reg [3:0] lines;

assign linesout = lines;

initial lines = 4'b0000;
always begin
#10 lines = 4'b1111;
#10 lines = 4'b0000;
end

endmodule

Perhaps?
I'm wondering how to trigger the always block, and also the Xilinx ISE
warning; 'Delay is ignored for synthesis.'


One waveform looks something like
__|--|__|---------|__|--|__|---------|__|--|__|---------|__|--|__|---------|

Thanks for any help.

 

[Jonathan Bromley]

On Wed, 16 May 2007 19:31:04 +1200,
JeffC <betchanz@yahoo.co.nz> wrote:

trying to generate four synchronized periodic digital waveforms (they
are not square or PWM) for output from my Spartan 3 FPGA.

Your code is perfectly legal Verilog and simulates OK (though I
don't quite see why it generates the waveform you doodled) - but
it is not synthesisable to hardware, which is why ISE whinged.
Also, it's poor style (for synthesis) to use an initial block
to reset a reg that will later be updated by an always block;
but I believe ISE will accept that style OK.

Good question about triggering the always block. In fact,
you should always (pun intended) start by using always blocks
that are clocked by your system clock. Note also the asynch
reset idiom, and the use of nonblocking (<=) assignment.
The latter is VERY important in clocked logic.

module waveforms(clock, reset, lines);

input clk;
output [3:0] lines;
reg [3:0] lines; // OK to use the output reg directly

// 6-bit address counter
reg [5:0] address;
always @(posedge clock or posedge asynch_reset)
if (asynch_reset) begin
// Asynch reset of all your registers, counters etc
address <= 0;
lines <= 0;
end else begin
// clocked actions that take place on each clock edge
address <= address + 1;
// here, fabricate your outputs as a function of the address
lines[3] <= address[5]; // just a slow square wave
lines[2] <= (address == 6'b100000); // 1-clk pulse at cycle 32
... <--- anything else you can think of !
end

endmodule // waveforms

You could also use the address to point into a blockRAM that
has been initialised with an interesting waveform lookup table,
and use the RAM's read-data as your outputs.

There are PLENTY more ways to make waveform generators, but that
simple table lookup or function generator should get you started.

Note that to test this design in simulation, you'll need a
test fixture (testbench) to provide the clock generator and
reset that, in the real world, would be part of your external
(development board?) hardware. Something like this...

module Wavegen_Tester;

// connections to device-under-test (DUT)
wire [3:0] waves;
reg clock, reset;

// instance of DUT
waveforms DUT(clock, reset, waves);

// clock generator, runs for 1000 cycles
initial begin
clock = 0;
repeat (2000) #5 clock = ~clock;
end // clock generator

// reset generator, one-shot at startup
initial begin
reset = 1;
#20 reset = 0;
end // reset generator

endmodule // Wavegen_Tester

You won't actually need a reset on your Xilinx part. Just
tie-off the module's reset input to ground (0) somewhere at
the top level, and the ISE software will work out what you
are doing and will arrange that the relevant registers get
configured to zero when you load the FPGA. But you *do* need
a reset in simulation; if it isn't there, all your hardware
registers will be stuck at X.

Good luck; let us know how you progress...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[JeffC]

Jonathan Bromley wrote:

On Wed, 16 May 2007 19:31:04 +1200,
JeffC <betchanz@yahoo.co.nz> wrote:

trying to generate four synchronized periodic digital waveforms (they
are not square or PWM) for output from my Spartan 3 FPGA.

snip

Good luck; let us know how you progress...

Wow, thanks for the excellent post Jonathan. I very much appreciate it.