Z
zwalter
Guest
Hello!
I read that the MPMC memory controller sends automaticly (1us period
periodic read request to the DDR3 module to measure the phase detection
(http://www.xilinx.com/support/answers/36719.htm -> Disabling Periodi
Reads During Writes)
I don't understand, that if the module is red in every 1us, than why is
refresh logic implemented in the mpmc module? I think with every read th
content of a memory cell is refreshed.
In my work I want to measure memory retention time. I have modified th
refresh logic of the MPMC module. I have set non JEDEC refresh times, t
get memory data loss.
However I tested my system on a Virtex 6 board, and at very large refres
period, the written data in the memory remains, without any loss.
Thank you for the answers!
Walter
---------------------------------------
Posted through http://www.FPGARelated.com
I read that the MPMC memory controller sends automaticly (1us period
periodic read request to the DDR3 module to measure the phase detection
(http://www.xilinx.com/support/answers/36719.htm -> Disabling Periodi
Reads During Writes)
I don't understand, that if the module is red in every 1us, than why is
refresh logic implemented in the mpmc module? I think with every read th
content of a memory cell is refreshed.
In my work I want to measure memory retention time. I have modified th
refresh logic of the MPMC module. I have set non JEDEC refresh times, t
get memory data loss.
However I tested my system on a Virtex 6 board, and at very large refres
period, the written data in the memory remains, without any loss.
Thank you for the answers!
Walter
---------------------------------------
Posted through http://www.FPGARelated.com