Peace of code

[Luiz Gustavo]

What this instructions means?


reg [2:0] SCKr;

always @(posedge clk) SCKr <= {SCKr[1:0], SCK};

wire SCK_risingedge = (SCKr[2:1]==2'b01); // I don't understand this
part of wire.....
wire SCK_fallingedge = (SCKr[2:1]==2'b10);

// how it's possible to associate two bits of a register to a wire???

 

[gabor]

On Dec 12, 1:27 pm, Luiz Gustavo <luizval...@gmail.com> wrote:

What this instructions means?

reg [2:0] SCKr;

always @(posedge clk) SCKr <= {SCKr[1:0], SCK};

wire SCK_risingedge = (SCKr[2:1]==2'b01); // I don't understand this
part of wire.....
wire SCK_fallingedge = (SCKr[2:1]==2'b10);

// how it's possible to associate two bits of a register to a wire???

The wire is assigned to the output of the equality comparison, not
the two bits of the register.

SCKr is a 3-bit shift register.

SCK_risingedge decodes a 0 to 1 transition on SCK one clock cycle
later.

SCK_fallingedge decodes a 1 to 0 transition on SCK one clock cycle
later.