pcix core in XC2VP7

[Matthias Müller]

Hello,
I'm developing a pcix-card and I will use the PCIX-core from Xilinx in a
XC2VP7-5FF896 FPGA. Does anyone know if there is the need for using
special pins of the FPGA to connecet the PCIX-signals to the
bus-connector. Or can I use any FPGA-pin for any PCIX-signal?
Thank you for answers!
Matthias Müller

**************
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[Mark Schellhorn]

Check out answer record #14965:

http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14965

The databook I have (older) mentioned some banking restrictions but it looks
like they have disappeared with newer software.

Make sure you obey the PCI-X trace length restrictions on the card. I would
establish the orientation of your FPGA on the card and then choose a pinout that
lines up with the edge card pins. Worked for me.

Mark


Matthias Müller wrote:

Hello,
I'm developing a pcix-card and I will use the PCIX-core from Xilinx in a
XC2VP7-5FF896 FPGA. Does anyone know if there is the need for using
special pins of the FPGA to connecet the PCIX-signals to the
bus-connector. Or can I use any FPGA-pin for any PCIX-signal?
Thank you for answers!
Matthias Müller

**************
Please remove the *no*spam* from my email-address, if you want to mail
to me!

 

[Muthu]

Matthias Müller <mur@iis.fhg.de> wrote in message news:<3FE81731.2EDF3DE9@iis.fhg.de>...

Hello,
I'm developing a pcix-card and I will use the PCIX-core from Xilinx in a
XC2VP7-5FF896 FPGA. Does anyone know if there is the need for using
special pins of the FPGA to connecet the PCIX-signals to the
bus-connector. Or can I use any FPGA-pin for any PCIX-signal?
Thank you for answers!
Matthias Müller

**************
Please remove the *no*spam* from my email-address, if you want to mail
to me!

Hi,

You should use the PCIX IOs listed in Datasheet.

These IOs meet the PCIX specification standards.

Regards,
Muthu

 

[Matthias Müller]

Thank you!
Looks like any user I/O can be used with the pci-x standard.
Have you considered the XAPP653 for over- and undershoot handling?
Xilinx recommends to regulate Vcco to 3.0V for all banks with pci-x standard in order to keep
values within the maximum FPGA specification.

Matthias


Mark Schellhorn schrieb:

Check out answer record #14965:

http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14965

The databook I have (older) mentioned some banking restrictions but it looks
like they have disappeared with newer software.

Make sure you obey the PCI-X trace length restrictions on the card. I would
establish the orientation of your FPGA on the card and then choose a pinout that
lines up with the edge card pins. Worked for me.

Mark

Matthias Müller wrote:
Hello,
I'm developing a pcix-card and I will use the PCIX-core from Xilinx in a
XC2VP7-5FF896 FPGA. Does anyone know if there is the need for using
special pins of the FPGA to connecet the PCIX-signals to the
bus-connector. Or can I use any FPGA-pin for any PCIX-signal?
Thank you for answers!
Matthias Müller

**************
Please remove the *no*spam* from my email-address, if you want to mail
to me!

--
Matthias Müller
Fraunhofer Institut Integrierte Schaltungen IIS
-Bildsensorik-
Am Wolfsmantel 33
D-91058 Erlangen
Tel: +49 (0)9131-776-554
Fax: +49 (0)9131-776-598
mailto:mur@iis.fhg.de http://www.iis.fhg.de