pci-x core

[Matthias Müller]

Hi all,
Doeas anyone know if the Xilinx PCI-X core includes pinout constraints,
so it is determined which PCI-X signal is connected to which pin of a
certain package (e.g. FF1517) ?
I don't have the core documentation yet and until now I have arranged
the pinout according to the connector-signal arrangement in order to
minimize trace lengths.
Thank you for answers.
Matthias


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[Mark Schellhorn]

In includes some example UCF files for different device/package combinations
that are known to meet timing when you implement them. The latest build includes
files for 2vp7ff672, 2v1000-fg456, and v300ebg432 devices.

You don't have to use these. I am working into a 2v500-fg456 and have no problem
meeting timing. I chose my pinout to line up nicely with the PCI card edge
fingers and minimize board track length and crossovers. I did create an
AREA_GROUP constraint for the XPCI_WRAP module in my design. It seems to meet
timing more easily if it has a smaller area to P&R in.

Mark

Matthias Müller wrote:

Hi all,
Doeas anyone know if the Xilinx PCI-X core includes pinout constraints,
so it is determined which PCI-X signal is connected to which pin of a
certain package (e.g. FF1517) ?
I don't have the core documentation yet and until now I have arranged
the pinout according to the connector-signal arrangement in order to
minimize trace lengths.
Thank you for answers.
Matthias


--
Please remove *spam* from my email address if you want to contact me.