PCI-X Core

[riet]

Hello all,

I would like your opinion on how long (in human hours) it would
take to do a project with the following deliverables:
1. a design of a PCI-X revision 1.0 core using VHDL,
2. an FPGA with the PCI-X core implemented on it,
3. a test bench implemented in VHDL,
4. a PCI-X card, that contains this FPGA and other peripheral hardware
for
testing purposes,
5. a driver that will access the PCI-X card via the PCI-X bus, and
6. a program that transfers data to and from the PCI-X card via the
driver.

Assume the following:
1. The PCI-X PCB, that works with a commercial PCI-X core (deliverable
4) is
provided.
2. Verilog code that implements a PCI core, like the core available
from
http://www.opencores.org, may be used.
3. This project is given to one graduate student in computer
engineering
with the VHDL experience of a one semester course in rapid
prototyping.
4. This student has full technical support from a company that
specialises
in digital design, in terms of advice, but all development should be
done
by the student.


I had to do this project and had say, four months full time and six
months
part time (3-4 hours/day) to do it.
I could not complete this project by a long shot. Now I'm just
wondering
if I were too stupid, or if the university was a bit(or a lot)
unreasonable.

Regards.

 

In which phase(s) of the project did you meet problems ?

The first big problem I see is that a Verilog IP core
is used by a VHDL person.

The second problem is you need to have some proper
simulation models to simulate the interface. Did you have any
experiences in writing testbenches before ?
How did you simuate the Verilog IP core with the VHDL testbench ?
Did you have the proper tools for that mixed language simulation ?

Can you go more into detail about the technical support from
the company ? What support did they actually offer to you ?

Rgds
André

 

[riet]

ALu...@web.de wrote:

In which phase(s) of the project did you meet problems ?
The setting is a subject in the final year of a graduate

computer engineering course called "Project 400". The idea of the
subject is to have students complete a project from start to
finish, to teach them how to use the proper systems engineering
process. This is the final "test" before the students are unleashed
into the "real world". So it's sort of playing "engineer-engineer"
with someone holding your hand in terms of directing you in the right
direction.

i.e.: I came in when the total documnetation of the system was:
"Design a PCI-X core in VHDL, including a testbench."
That's it.

The first big problem I see is that a Verilog IP core
is used by a VHDL person.
They actually wanted a complete VHDL solution. My studyleader said

I could either port the Verilog PCI stuff, or write it from scratch.
He felt it would take about the same time. I decided to port the code,
all +-30k lines of it. At that stage I wasn't really a "VHDL person"
more like someone who would recognise it when he saw it and could write
a simple ping pong game with an Altera UP2 development board. So I had
to learn VHDL and Verilog as a beginner.

In November 2003, when my final report had to be in, I only managed to
finish the porting excersise, including the testbench. The tests ran
to some extent, but there was still a lot of errors.

The second problem is you need to have some proper
simulation models to simulate the interface. Did you have any
experiences in writing testbenches before ?
None. I read up some tutorials on the web.

How did you simuate the Verilog IP core with the VHDL testbench ?
Did you have the proper tools for that mixed language simulation ?
See above. They did have proper tools for me to use, but I didn't get

to use them. (Can't remember the toolset)

Can you go more into detail about the technical support from
the company ? What support did they actually offer to you ?
Well, I could go sit in one of their offices. They already had a PCI

core that worked for the applications that they needed it for, but did
not have all the functionality the opencores one had. So there was
people
that knew the core. I would say the support(If I ever got so far to
make
use of it) would have included using their toolset (some seats only
after
hours since they only had one or two seats of some tools) and I would
have
been able to consult other engineers for say 4 to 8 hours per week.
Also they said when I finished the schematic of the card, someone there
would be given time to do the layout for me.

 

I decided to port the code, all +-30k lines of it.

Did you just port the code or did you try to understand how PCI works ?

Rgds
André

 

[riet]

ALuPin@web.de wrote:

Did you just port the code or did you try to understand how PCI works ?

For the first few months I spent all my time
to try to understand how PCI works. I wanted
to do it from scratch, from first principles.
After a while I became overwhelmed and started
to just try to understand the small modules I
was porting at the time. I understand the high
level concepts of PCI and PCI-X, but the
implementation was too much for me in the short
time.

I worked through the books PCI and PCI-X System
Architecture by Tom Shanly:

http://www.amazon.com/exec/obidos/tg/detail/-/0201726823/qid=1129044102/sr=1-1/ref=sr_1_1/002-8368389-9552833?v=glance&s=books

http://www.amazon.com/exec/obidos/tg/detail/-/0201309742/ref=pd_sr_ec_ir_b/002-8368389-9552833?v=glance&s=books&st=*

I also read both specifications (PCI & PCI-X) by the PCISIG.

Regards,
riet

 

[Kai Harrekilde-Petersen]

"riet" <jacques.viviers@gmail.com> writes:

Hello all,

I would like your opinion on how long (in human hours) it would
take to do a project with the following deliverables:
1. a design of a PCI-X revision 1.0 core using VHDL,
2. an FPGA with the PCI-X core implemented on it,
3. a test bench implemented in VHDL,
4. a PCI-X card, that contains this FPGA and other peripheral hardware
for
testing purposes,
5. a driver that will access the PCI-X card via the PCI-X bus, and
6. a program that transfers data to and from the PCI-X card via the
driver.

The PCI (and PCI-X) interfaces are rather complex. For someone to
first read up on PCI(-X) and then implement it, is at least a full
man-year's worth of work. The testbench is probably another 6 months.

I doubt you could get it to run 66+ MHz in an FPGA, given the level of
experience. Wringing the neck of an FPGA takes experience, and coding
exactly to get the desired performance.

At least, that's my experience (which is a few year old by now).


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

[riet]

Kai wrote:

The PCI (and PCI-X) interfaces are rather complex. For someone to
first read up on PCI(-X) and then implement it, is at least a full
man-year's worth of work. The testbench is probably another 6 months.

Would you say that this is for the synthesized simulations
and test only, or would it include the hardware implementation?
i.e.: From start to having a test application on a PC that uses
the implementation.

I doubt you could get it to run 66+ MHz in an FPGA, given the level of
experience. Wringing the neck of an FPGA takes experience, and coding
exactly to get the desired performance.

What do you think the project status would be after 640 hours?
(This was the time in which it was expected from me to fininsh
the project, including the documentation - complete data pack.)
Given my experience.

Regards,
riet

 

What do you think the project status would be after 640 hours?

How long takes F1 Alonso to drive 300km ? How long will it take if you
drive in your car ?

Difficult question, it all depends on your skills, experience and tools
....All things your professor
should know!


Rgds
André

 

[riet]

But would agree with me if I say that 640 hours was not
nearly enough to even reach the half-way mark? i.e.: To get
the PCI core and testbench written in VHDL working in synthesized
simulations. This for someone with about 100 hours VHDL experience
and 40 hours PCI(-X) experience.

What would you expect from an engineer with 1 year experience
in VHDL, if you had to contract him?

regards
riet