PCI-X bridge from Xilinx LogiCORE and half bridge

[Nahum Barnea]

Hi.
I'm considering Xilinx LogiCORE PCI-X core, and Xilinx HalfBridge core
for building a PCI-X bridge.

Can anyone share experience with these cores for PCI bridge
application ?
Does these cores deal with the address translation from "type 1" to
"type 0" ?

ThankX
NAHUM

 

[Eric Crabill]

Hello,

To get a better answer, you'll have to be more specific
about what you want to build. Are you trying to build a
fully compliant PCI(-X) to PCI(-X) bridge? If that is
the case, you should buy an ASSP to do the job.

The Xilinx PCI and PCI-X LogiCOREs, as you might buy them
over the web, have Type 0 configuration spaces and are not
suitable for compliant bridging applications. However,
there are other options and it depends on what you are
trying to do.

What exactly are you trying to do?
Eric

Hi.

I'm considering Xilinx LogiCORE PCI-X core, and Xilinx
HalfBridge core for building a PCI-X bridge.

Can anyone share experience with these cores for PCI bridge
application? Does these cores deal with the address
translation from "type 1" to "type 0" ?

ThankX
NAHUM

 

[Nahum Barnea]

Hi.
Well it is not just a bridge, and thats why I cant buy an ASSP.

In the Half Bridge application note from Xilinx, there is specific
chapter dealing with bridging between several PCI-X cores. I do not
need the core to be fully PCI bridge compliant, nor have PCI bridge
configuration header within it. What I need is that the core will
capture type 1 configuration cycles and reflect them on the user
application side of the core. In this way I could have my own logic to
translate those transactions to type 0 configuration transaction on
other busses I have connected to our FPGA.

ThankX,
NAHUM

Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3F8AF3B7.BFD97D10@xilinx.com>...

Hello,

To get a better answer, you'll have to be more specific
about what you want to build. Are you trying to build a
fully compliant PCI(-X) to PCI(-X) bridge? If that is
the case, you should buy an ASSP to do the job.

The Xilinx PCI and PCI-X LogiCOREs, as you might buy them
over the web, have Type 0 configuration spaces and are not
suitable for compliant bridging applications. However,
there are other options and it depends on what you are
trying to do.

What exactly are you trying to do?
Eric

Hi.

I'm considering Xilinx LogiCORE PCI-X core, and Xilinx
HalfBridge core for building a PCI-X bridge.

Can anyone share experience with these cores for PCI bridge
application? Does these cores deal with the address
translation from "type 1" to "type 0" ?

ThankX
NAHUM

 

[Eric Crabill]

Hello,

Well it is not just a bridge, and thats why I cant buy an ASSP.

Fair enough.

In the Half Bridge application note from Xilinx, there is specific
chapter dealing with bridging between several PCI-X cores. I do not
need the core to be fully PCI bridge compliant, nor have PCI bridge
configuration header within it. What I need is that the core will
capture type 1 configuration cycles and reflect them on the user
application side of the core. In this way I could have my own logic
to translate those transactions to type 0 configuration transaction
on other busses I have connected to our FPGA.

The Xilinx PCI and PCI-X LogiCORE products do not accept Type 1
configuration cycles. They can, however, generate both Type 1
and Type 0 configuration cycles. This makes them suitable for
host bridge designs. It makes them unsuitable for the type of
design you described.

You may ask, then, what the application note is referring to when
it discusses bridging bus segments. That application is for making
a "cross-link" bridge between two bus segments, where there is
already a host for each segment. I will admit that the document
is not entirely clear on this point, and I have asked the authors
to correct the application note.

If you are interested in pursuing your desired application, you
should contact your Xilinx FAE, who will be able to assist you.

Good luck,
Eric

Hello,

To get a better answer, you'll have to be more specific
about what you want to build. Are you trying to build a
fully compliant PCI(-X) to PCI(-X) bridge? If that is
the case, you should buy an ASSP to do the job.

The Xilinx PCI and PCI-X LogiCOREs, as you might buy them
over the web, have Type 0 configuration spaces and are not
suitable for compliant bridging applications. However,
there are other options and it depends on what you are
trying to do.

What exactly are you trying to do?
Eric

Hi.

I'm considering Xilinx LogiCORE PCI-X core, and Xilinx
HalfBridge core for building a PCI-X bridge.

Can anyone share experience with these cores for PCI bridge
application? Does these cores deal with the address
translation from "type 1" to "type 0" ?

Thankx
NAHUM

 

[Nahum Barnea]

Hi Eric,

How will the core behave if the host will issue a type 1 configuration
cycle while selecting the xilinx device with IDSEL?

Can my internal logic sniff configuration transaction on the PCI bus?

ThankX,
NAHUM


Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<3F8C5BF0.CBC8810E@xilinx.com>...

Hello,

Well it is not just a bridge, and thats why I cant buy an ASSP.

Fair enough.

In the Half Bridge application note from Xilinx, there is specific
chapter dealing with bridging between several PCI-X cores. I do not
need the core to be fully PCI bridge compliant, nor have PCI bridge
configuration header within it. What I need is that the core will
capture type 1 configuration cycles and reflect them on the user
application side of the core. In this way I could have my own logic
to translate those transactions to type 0 configuration transaction
on other busses I have connected to our FPGA.

The Xilinx PCI and PCI-X LogiCORE products do not accept Type 1
configuration cycles. They can, however, generate both Type 1
and Type 0 configuration cycles. This makes them suitable for
host bridge designs. It makes them unsuitable for the type of
design you described.

You may ask, then, what the application note is referring to when
it discusses bridging bus segments. That application is for making
a "cross-link" bridge between two bus segments, where there is
already a host for each segment. I will admit that the document
is not entirely clear on this point, and I have asked the authors
to correct the application note.

If you are interested in pursuing your desired application, you
should contact your Xilinx FAE, who will be able to assist you.

Good luck,
Eric

Hello,

To get a better answer, you'll have to be more specific
about what you want to build. Are you trying to build a
fully compliant PCI(-X) to PCI(-X) bridge? If that is
the case, you should buy an ASSP to do the job.

The Xilinx PCI and PCI-X LogiCOREs, as you might buy them
over the web, have Type 0 configuration spaces and are not
suitable for compliant bridging applications. However,
there are other options and it depends on what you are
trying to do.

What exactly are you trying to do?
Eric

Hi.

I'm considering Xilinx LogiCORE PCI-X core, and Xilinx
HalfBridge core for building a PCI-X bridge.

Can anyone share experience with these cores for PCI bridge
application? Does these cores deal with the address
translation from "type 1" to "type 0" ?

Thankx
NAHUM

 

[Eric Crabill]

Hello,

How will the core behave if the host will issue a type 1
config cycle while selecting the xilinx device with IDSEL?

It will ignore the cycle, because it was designed to do so.

Can my internal logic sniff configuration transaction
on the PCI bus?

Not really. The v3.0 core has some provision to do things like
this, but the v5.0 core does not. Plus, even if you could, the
configuration mechanism will not work properly. What if you
need to do a config read? Snooping won't help, because you
need to actively participate in the transaction.

If you contact your Xilinx FAE, and indicate you need to do a
PCI bridging application, they can help you.

Eric