PCI Timings

[Sylvain Munaut]

Hi

I'm trying to understand the PCI specifications, and there are some timings specs I don't understand.

They say that :

* For output:
t_val is CLK to output valid : min 2ns max 11ns

* For input:
t_su is Setup time beforce CLK : min 7ns
t_h is Hold time after CLK : min 0ns

* At 33Mhz, clk period is 30ns


What is an input for one chip of the bus is an output for another one.
So :
Why does t_val need to be min 2ns ? For the one that samples the signal, t_h must be 0ns.
Why max 11ns ? Since setup time is min 7ns ...
Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle.



Sylvain Munaut

 

[Hal Murray]

What is an input for one chip of the bus is an output for another one.
So :
Why does t_val need to be min 2ns ? For the one that samples the signal, t_h must be 0ns.
Why max 11ns ? Since setup time is min 7ns ...
Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle.

The differences in times from what you might quickly calculate cover
two areas. One is clock skew between the chips. The other is the time
for the signal to get from one chip to the other. With several chips
on a "bus", that can be a lot longer than the simple speed of light delays.

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[Sylvain Munaut]

Hal Murray wrote:

What is an input for one chip of the bus is an output for another one.
So :
Why does t_val need to be min 2ns ? For the one that samples the signal, t_h must be 0ns.
Why max 11ns ? Since setup time is min 7ns ...
Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle.


The differences in times from what you might quickly calculate cover
two areas. One is clock skew between the chips. The other is the time
for the signal to get from one chip to the other. With several chips
on a "bus", that can be a lot longer than the simple speed of light delays.

Ok, so that means that the output of my FPGA must be stable for at least 2ns after receiving the clock and then change before 11ns after clock.
How can I ensure that in my VHDL code ...



Sylvain Munaut

 

[Vaughn Betz]

Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<ccpkhu$9i8$1@ail.sri.ucl.ac.be>...

Hal Murray wrote:
What is an input for one chip of the bus is an output for another one.
So :
Why does t_val need to be min 2ns ? For the one that samples the signal, t_h must be 0ns.
Why max 11ns ? Since setup time is min 7ns ...
Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle.


The differences in times from what you might quickly calculate cover
two areas. One is clock skew between the chips. The other is the time
for the signal to get from one chip to the other. With several chips
on a "bus", that can be a lot longer than the simple speed of light delays.


Ok, so that means that the output of my FPGA must be stable for at least 2ns after receiving the clock and then change before 11ns after clock.
How can I ensure that in my VHDL code ...



Sylvain Munaut

Hi Sylvain,

You can't ensure that happens just by coding your VHDL in a certain
way. You need to set appropriate timing constraints to ensure that
synthesis, placement and routing all work on the proper paths, and
achieve the desired delays. The precise syntax varies from tool to
tool.

For Altera's CAD suite (Quartus), you would use the assignment editor
to set

Tco 11 ns
minTco 2 ns
Tsu 7 ns
Th 0 ns

That would set these constraints for every IO in the design. If you
want different constraints for different IOs, you make assignments to
specific IOs.

You should also the timing settings dialog to make a clock frequency
setting of 33 MHz to your PCI clock.

If you really want to set these constraints in your VHDL, you can by
embedding the constraints in the Quartus Tcl command format as
comments in your VHDL. See the Quartus help for the details of this
format.

Quartus will try to get short routes for signals on Tsu or Tco
critical paths. For paths that are in danger of failing their Th or
minTco constraints, Quartus will add routing delay to slow them down.

You have to code your VHDL so that it is possible to meet your timing
constraints. For 33 MHz PCI that isn't too hard. Make sure you don't
put logic after your output registers, and make sure you don't put any
more logic than you need on the Tsu-critical paths (from input IO to
registers).

Regards,

Vaughn
Altera